diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2015-05-25 22:35:04 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-06-04 02:39:39 -0600 |
| commit | 9c7dea602edd9027848d312e9b3b69f06c15f163 (patch) | |
| tree | 4893732c170a3a889b819482f7003491ecbac11c /lib/fdtdec.c | |
| parent | 2aa3a7fb1c24afd4c0e12360acccf3234d8fe019 (diff) | |
x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'lib/fdtdec.c')
| -rw-r--r-- | lib/fdtdec.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/fdtdec.c b/lib/fdtdec.c index b586da2a56..1808350a57 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -77,6 +77,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"), COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"), + COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) |