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| author | Mike Dunn <mikedunn@newsguy.com> | 2013-06-21 09:12:28 -0700 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2013-06-22 15:25:28 +0200 |
| commit | 9dc8fef2583f23ca6a99c6f5e709a8b80018364f (patch) | |
| tree | 7bcd2987166a8f966dcfc4e4610376d7f061ea36 /nand_spl/nand_boot_fsl_elbc.c | |
| parent | 84c617beb2ddcda03e36abe553432e2784ada6b7 (diff) | |
pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled. Tested
on the pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Diffstat (limited to 'nand_spl/nand_boot_fsl_elbc.c')
0 files changed, 0 insertions, 0 deletions