Extend POST support for PPC440

Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--

5 files changed, 541 insertions, 0 deletions

diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile
new file mode 100644
index 0000000000..8e8ab50577
--- /dev/null
+++ b/post/cpu/ppc4xx/Makefile
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LIB	= libpostppc4xx.a
+
+COBJS	= fpu.o spr.o uart.o watchdog.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
new file mode 100644
index 0000000000..1935c011ba
--- /dev/null
+++ b/post/cpu/ppc4xx/fpu.c
@@ -0,0 +1,55 @@
+/*
+ *  Copyright (C) 2007 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_POST
+#if defined(CONFIG_440EP) || \
+    defined(CONFIG_440EPX)
+
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+int fpu_status(void)
+{
+	if (mfspr(ccr0) & CCR0_DAPUIB)
+		return 0; /* Disabled */
+	else
+		return 1; /* Enabled */
+}
+
+
+void fpu_disable(void)
+{
+	mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
+	mtmsr(mfmsr() & ~MSR_FP);
+}
+
+
+void fpu_enable(void)
+{
+	mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
+	mtmsr(mfmsr() | MSR_FP);
+}
+#endif
+#endif
diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
new file mode 100644
index 0000000000..f62526a171
--- /dev/null
+++ b/post/cpu/ppc4xx/spr.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * SPR test
+ *
+ * The test checks the contents of Special Purpose Registers (SPR) listed
+ * in the spr_test_list array below.
+ * Each SPR value is read using mfspr instruction, some bits are masked
+ * according to the table and the resulting value is compared to the
+ * corresponding table value.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_SPR
+
+static struct
+{
+    int number;
+    char * name;
+    unsigned long mask;
+    unsigned long value;
+} spr_test_list [] = {
+	/* Standard Special-Purpose Registers */
+
+	{0x001,	"XER",		0x00000000,	0x00000000},
+	{0x008,	"LR",		0x00000000,	0x00000000},
+	{0x009,	"CTR",		0x00000000,	0x00000000},
+	{0x016,	"DEC",		0x00000000,	0x00000000},
+	{0x01a,	"SRR0",		0x00000000,	0x00000000},
+	{0x01b,	"SRR1",		0x00000000,	0x00000000},
+	{0x110,	"SPRG0",	0x00000000,	0x00000000},
+	{0x111,	"SPRG1",	0x00000000,	0x00000000},
+	{0x112,	"SPRG2",	0x00000000,	0x00000000},
+	{0x113,	"SPRG3",	0x00000000,	0x00000000},
+	{0x11f,	"PVR",		0x00000000,	0x00000000},
+
+	/* Additional Special-Purpose Registers */
+
+	{0x30,	"PID",		0x00000000,	0x00000000},
+	{0x3a,	"CSRR0",	0x00000000,	0x00000000},
+	{0x3b,	"CSRR1",	0x00000000,	0x00000000},
+	{0x3d,	"DEAR",		0x00000000,	0x00000000},
+	{0x3e,	"ESR",		0x00000000,	0x00000000},
+	{0x3f,	"IVPR",		0xffff0000,	0x00000000},
+	{0x100,	"USPRG0",	0x00000000,	0x00000000},
+	{0x104,	"SPRG4",	0x00000000,	0x00000000},
+	{0x105,	"SPRG5",	0x00000000,	0x00000000},
+	{0x106,	"SPRG6",	0x00000000,	0x00000000},
+	{0x107,	"SPRG7",	0x00000000,	0x00000000},
+	{0x10c,	"TBL",		0x00000000,	0x00000000},
+	{0x10d,	"TBU",		0x00000000,	0x00000000},
+	{0x11e,	"PIR",		0x0000000f,	0x00000000},
+	{0x130,	"DBSR",		0x00000000,	0x00000000},
+	{0x134,	"DBCR0",	0x00000000,	0x00000000},
+	{0x135,	"DBCR1",	0x00000000,	0x00000000},
+	{0x136,	"DBCR2",	0x00000000,	0x00000000},
+	{0x138,	"IAC1",		0x00000000,	0x00000000},
+	{0x139,	"IAC2",		0x00000000,	0x00000000},
+	{0x13a,	"IAC3",		0x00000000,	0x00000000},
+	{0x13b,	"IAC4",		0x00000000,	0x00000000},
+	{0x13c,	"DAC1",		0x00000000,	0x00000000},
+	{0x13d,	"DAC2",		0x00000000,	0x00000000},
+	{0x13e,	"DVC1",		0x00000000,	0x00000000},
+	{0x13f,	"DVC2",		0x00000000,	0x00000000},
+	{0x150,	"TSR",		0x00000000,	0x00000000},
+	{0x154,	"TCR",		0x00000000,	0x00000000},
+	{0x190,	"IVOR0",	0x00000000,	0x00000000},
+	{0x191,	"IVOR1",	0x00000000,	0x00000000},
+	{0x192,	"IVOR2",	0x00000000,	0x00000000},
+	{0x193,	"IVOR3",	0x00000000,	0x00000000},
+	{0x194,	"IVOR4",	0x00000000,	0x00000000},
+	{0x195,	"IVOR5",	0x00000000,	0x00000000},
+	{0x196,	"IVOR6",	0x00000000,	0x00000000},
+	{0x197,	"IVOR7",	0x00000000,	0x00000000},
+	{0x198,	"IVOR8",	0x00000000,	0x00000000},
+	{0x199,	"IVOR9",	0x00000000,	0x00000000},
+	{0x19a,	"IVOR10",	0x00000000,	0x00000000},
+	{0x19b,	"IVOR11",	0x00000000,	0x00000000},
+	{0x19c,	"IVOR12",	0x00000000,	0x00000000},
+	{0x19d,	"IVOR13",	0x00000000,	0x00000000},
+	{0x19e,	"IVOR14",	0x00000000,	0x00000000},
+	{0x19f,	"IVOR15",	0x00000000,	0x00000000},
+	{0x23a,	"MCSRR0",	0x00000000,	0x00000000},
+	{0x23b,	"MCSRR1",	0x00000000,	0x00000000},
+	{0x23c,	"MCSR",		0x00000000,	0x00000000},
+	{0x370,	"INV0",		0x00000000,	0x00000000},
+	{0x371,	"INV1",		0x00000000,	0x00000000},
+	{0x372,	"INV2",		0x00000000,	0x00000000},
+	{0x373,	"INV3",		0x00000000,	0x00000000},
+	{0x374,	"ITV0",		0x00000000,	0x00000000},
+	{0x375,	"ITV1",		0x00000000,	0x00000000},
+	{0x376,	"ITV2",		0x00000000,	0x00000000},
+	{0x377,	"ITV3",		0x00000000,	0x00000000},
+	{0x378,	"CCR1",		0x00000000,	0x00000000},
+	{0x390,	"DNV0",		0x00000000,	0x00000000},
+	{0x391,	"DNV1",		0x00000000,	0x00000000},
+	{0x392,	"DNV2",		0x00000000,	0x00000000},
+	{0x393,	"DNV3",		0x00000000,	0x00000000},
+	{0x394,	"DTV0",		0x00000000,	0x00000000},
+	{0x395,	"DTV1",		0x00000000,	0x00000000},
+	{0x396,	"DTV2",		0x00000000,	0x00000000},
+	{0x397,	"DTV3",		0x00000000,	0x00000000},
+	{0x398,	"DVLIM",	0x00000000,	0x00000000},
+	{0x399,	"IVLIM",	0x00000000,	0x00000000},
+	{0x39b,	"RSTCFG",	0x00000000,	0x00000000},
+	{0x39c,	"DCDBTRL",	0x00000000,	0x00000000},
+	{0x39d,	"DCDBTRH",	0x00000000,	0x00000000},
+	{0x39e,	"ICDBTRL",	0x00000000,	0x00000000},
+	{0x39f,	"ICDBTRH",	0x00000000,	0x00000000},
+	{0x3b2,	"MMUCR",	0x00000000,	0x00000000},
+	{0x3b3,	"CCR0",		0x00000000,	0x00000000},
+	{0x3d3,	"ICDBDR",	0x00000000,	0x00000000},
+	{0x3f3,	"DBDR",		0x00000000,	0x00000000},
+};
+
+static int spr_test_list_size =
+		sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+
+int spr_post_test (int flags)
+{
+	int ret = 0;
+	int i;
+
+	unsigned long code[] = {
+		0x7c6002a6,				/* mfspr r3,SPR */
+		0x4e800020				/* blr          */
+	};
+	unsigned long (*get_spr) (void) = (void *) code;
+
+	for (i = 0; i < spr_test_list_size; i++) {
+		int num = spr_test_list[i].number;
+
+		/* mfspr r3,num */
+		code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
+
+		asm volatile ("isync");
+
+		if ((get_spr () & spr_test_list[i].mask) !=
+			(spr_test_list[i].value & spr_test_list[i].mask)) {
+			post_log ("The value of %s special register "
+				  "is incorrect: 0x%08X\n",
+					spr_test_list[i].name, get_spr ());
+			ret = -1;
+		}
+	}
+
+	return ret;
+}
+#endif /* CONFIG_POST & CFG_POST_SPR */
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c
new file mode 100644
index 0000000000..f220dba17a
--- /dev/null
+++ b/post/cpu/ppc4xx/uart.c
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * UART test
+ *
+ * The controllers are configured to loopback mode and several
+ * characters are transmitted.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+
+#if CONFIG_POST & CFG_POST_UART
+
+#include <asm/processor.h>
+#include <serial.h>
+
+#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
+#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000500
+#define UART3_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#define UDIV_SUBTRACT	0
+#define UART0_SDR	sdr_uart0
+#define UART1_SDR	sdr_uart1
+#define UART2_SDR	sdr_uart2
+#define UART3_SDR	sdr_uart3
+#define MFREG(a, d)	mfsdr(a, d)
+#define MTREG(a, d)	mtsdr(a, d)
+
+#define UART_RBR    0x00
+#define UART_THR    0x00
+#define UART_IER    0x01
+#define UART_IIR    0x02
+#define UART_FCR    0x02
+#define UART_LCR    0x03
+#define UART_MCR    0x04
+#define UART_LSR    0x05
+#define UART_MSR    0x06
+#define UART_SCR    0x07
+#define UART_DLL    0x00
+#define UART_DLM    0x01
+
+/*
+  Line Status Register.
+*/
+#define asyncLSRDataReady1            0x01
+#define asyncLSROverrunError1         0x02
+#define asyncLSRParityError1          0x04
+#define asyncLSRFramingError1         0x08
+#define asyncLSRBreakInterrupt1       0x10
+#define asyncLSRTxHoldEmpty1          0x20
+#define asyncLSRTxShiftEmpty1         0x40
+#define asyncLSRRxFifoError1          0x80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int uart_post_init (unsigned long dev_base)
+{
+	unsigned long reg;
+	unsigned long udiv;
+	unsigned short bdiv;
+	volatile char val;
+#ifdef CFG_EXT_SERIAL_CLOCK
+	unsigned long tmp;
+#endif
+	int i;
+
+	for (i = 0; i < 3500; i++) {
+		if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
+			break;
+		udelay (100);
+	}
+	MFREG(UART0_SDR, reg);
+	reg &= ~CR0_MASK;
+
+#ifdef CFG_EXT_SERIAL_CLOCK
+	reg |= CR0_EXTCLK_ENA;
+	udiv = 1;
+	tmp  = gd->baudrate * 16;
+	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+#else
+	/* For 440, the cpu clock is on divider chain A, UART on divider
+	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
+	 * values that are subject to the 1/2 opb clock constraint
+	 */
+	serial_divs (gd->baudrate, &udiv, &bdiv);
+#endif
+
+	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
+
+	/*
+	 * Configure input clock to baudrate generator for all
+	 * available serial ports here
+	 */
+	MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+	MTREG(UART1_SDR, reg);
+#endif
+#if defined(UART2_SDR)
+	MTREG(UART2_SDR, reg);
+#endif
+#if defined(UART3_SDR)
+	MTREG(UART3_SDR, reg);
+#endif
+
+	out8(dev_base + UART_LCR, 0x80);	/* set DLAB bit */
+	out8(dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8(dev_base + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
+	out8(dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8(dev_base + UART_FCR, 0x00);	/* disable FIFO */
+	out8(dev_base + UART_MCR, 0x10);	/* enable loopback mode */
+	val = in8(dev_base + UART_LSR);		/* clear line status */
+	val = in8(dev_base + UART_RBR);		/* read receive buffer */
+	out8(dev_base + UART_SCR, 0x00);	/* set scratchpad */
+	out8(dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
+
+	return 0;
+}
+
+static void uart_post_putc (unsigned long dev_base, char c)
+{
+	int i;
+
+	out8 (dev_base + UART_THR, c);	/* put character out */
+
+	/* Wait for transfer completion */
+	for (i = 0; i < 3500; i++) {
+		if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
+			break;
+		udelay (100);
+	}
+}
+
+static int uart_post_getc (unsigned long dev_base)
+{
+	int i;
+
+	/* Wait for character available */
+	for (i = 0; i < 3500; i++) {
+		if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
+			break;
+		udelay (100);
+	}
+	return 0xff & in8 (dev_base + UART_RBR);
+}
+
+static int test_ctlr (unsigned long dev_base, int index)
+{
+	int res = -1;
+	char test_str[] = "*** UART Test String ***\r\n";
+	int i;
+
+	uart_post_init (dev_base);
+
+	for (i = 0; i < sizeof (test_str) - 1; i++) {
+		uart_post_putc (dev_base, test_str[i]);
+		if (uart_post_getc (dev_base) != test_str[i])
+			goto done;
+	}
+	res = 0;
+done:
+	if (res)
+		post_log ("uart%d test failed\n", index);
+
+	return res;
+}
+
+int uart_post_test (int flags)
+{
+	int i, res = 0;
+	static unsigned long base[] = {
+		UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
+	};
+
+	for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
+		if (test_ctlr (base[i], i))
+			res = -1;
+	}
+	serial_reinit_all ();
+
+	return res;
+}
+
+#endif /* CONFIG_POST & CFG_POST_UART */
+
+#endif /* CONFIG_POST */
diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c
new file mode 100644
index 0000000000..3c76cfd348
--- /dev/null
+++ b/post/cpu/ppc4xx/watchdog.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Watchdog test
+ *
+ * The test verifies the watchdog timer operation.
+ * On the first iteration, the test routine disables interrupts and
+ * makes a 10-second delay. If the system does not reboot during this delay,
+ * the watchdog timer is not operational and the test fails. If the system
+ * reboots, on the second iteration the test routine reports a success.
+ */
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CFG_POST_WATCHDOG
+
+int watchdog_post_test (int flags)
+{
+	if (flags & POST_REBOOT) {
+		/* Test passed */
+
+		return 0;
+	} else {
+		/* 10-second delay */
+		int ints = disable_interrupts ();
+		ulong base = post_time_ms (0);
+
+		while (post_time_ms (base) < 10000)
+			;
+		if (ints)
+			enable_interrupts ();
+
+		/*
+		 * If we have reached this point, the watchdog timer
+		 * does not work
+		 */
+		return -1;
+	}
+}
+
+#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
+#endif /* CONFIG_POST */