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author | Lokesh Vutla <lokeshvutla@ti.com> | 2017-12-28 20:40:01 +0530 |
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committer | Tom Rini <trini@konsulko.com> | 2018-01-19 15:49:24 -0500 |
commit | 9b88a4bda2955b23262736d70e5c3d3c36685db0 (patch) | |
tree | 56be0a56d3509e7c5a7a1f8a619aaff07ec540a1 /scripts/cleanpatch | |
parent | 3a0e70f181ecf21db2486c289055d4269887cab8 (diff) |
arm: am33xx: Avoid writing into reserved DPLL divider
DPLL DRR doesn't have an M4 divider. But the clock driver is trying
to configure M4 divider as 4(writing into a reserved register).
Fixing it by making M4 divider as -1.
Reported-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'scripts/cleanpatch')
0 files changed, 0 insertions, 0 deletions