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authorKever Yang <kever.yang@rock-chips.com>2019-04-02 20:41:23 +0800
committerKever Yang <kever.yang@rock-chips.com>2019-05-08 17:34:12 +0800
commit5793e8c271f73da2ca50fa3d57d3fea7e3d2796c (patch)
tree83dbf49c8756a857bbe557980544d924fc94483b /scripts/fill_scrapyard.py
parente4d0d61275ac1b14375be8f62585398e05b19f3f (diff)
rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'scripts/fill_scrapyard.py')
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