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| author | Tom Rini <trini@konsulko.com> | 2020-08-25 10:24:40 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-08-25 13:38:29 -0400 |
| commit | 9f9ecd3e4d7839e24c182fb7b24937e19b670f1b (patch) | |
| tree | 4250ad58dba47ae6127d4129b9a19dc648fd064d /test | |
| parent | ec54217ddc6f52f3b7dad7a3fd6d8a3abd64ab7e (diff) | |
| parent | 6944937f9c4d21f39dd257bce7b677a0f6849cea (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Add basic Marvell/Cavium OcteonTX/TX2 support (Suneel)
- Infrastructure changes to PCI uclass to support these SoC's (Suneel)
- Add PCI, MMC & watchdog driver drivers for OcteonTX/TX2 (Suneel)
- Increase CONFIG_SYS_MALLOC_F_LEN for qemu-x86 (Stefan)
Diffstat (limited to 'test')
| -rw-r--r-- | test/dm/pci.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/dm/pci.c b/test/dm/pci.c index fd66ed7899..76490befdf 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -354,3 +354,25 @@ static int dm_test_pci_on_bus(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* + * Test support for multiple memory regions enabled via + * CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled, + * only the last region of one type is stored. In this test-case, + * we have 2 memory regions, the first at 0x3000.0000 and the 2nd + * at 0x3100.0000. A correct test results now in BAR1 located at + * 0x3000.0000. + */ +static int dm_test_pci_region_multi(struct unit_test_state *uts) +{ + struct udevice *dev; + ulong mem_addr; + + /* Test memory BAR1 on bus#1 */ + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev)); + mem_addr = dm_pci_read_bar32(dev, 1); + ut_asserteq(mem_addr, 0x30000000); + + return 0; +} +DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); |