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authorLey Foon Tan <ley.foon.tan@intel.com>2019-11-27 15:55:21 +0800
committerMarek Vasut <marex@denx.de>2020-01-07 14:38:33 +0100
commit20322cea64e471c777627622e9ccb1096b5db167 (patch)
treef36ad30afa9a90b995ab15b45186808e9863ddab /tools/mrvl_uart.sh
parent38229994affe422ef202c574759a08a97e44317c (diff)
arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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