diff options
| -rw-r--r-- | include/configs/B4860QDS.h | 2 | ||||
| -rw-r--r-- | include/configs/T102xQDS.h | 2 | ||||
| -rw-r--r-- | include/configs/T1040QDS.h | 2 | ||||
| -rw-r--r-- | include/configs/T208xQDS.h | 2 | ||||
| -rw-r--r-- | include/configs/T4240QDS.h | 2 | ||||
| -rw-r--r-- | include/configs/T4240RDB.h | 2 | ||||
| -rw-r--r-- | include/fsl_ifc.h | 10 |
7 files changed, 11 insertions, 11 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index f758ea7dbe..252e1272c3 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -276,7 +276,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 42bfd07f58..f3b0fe0144 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -290,7 +290,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7d90797b08..2d5c96f335 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -215,7 +215,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 833a0608bf..1dcf2779d7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -266,7 +266,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 34b3b056ec..06939015d0 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -191,7 +191,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index f5eed0923f..42252c7c42 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -460,7 +460,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 8120ca0de8..17697c7341 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -70,7 +70,7 @@ #define IFC_AMASK_MASK 0xFFFF0000 #define IFC_AMASK_SHIFT 16 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) + (LOG2(n) - IFC_AMASK_SHIFT)) /* * Chip Select Option Register IFC_NAND Machine @@ -111,7 +111,7 @@ /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) /* Time for Read Enable High to Output High Impedance */ #define CSOR_NAND_TRHZ_MASK 0x0000001C #define CSOR_NAND_TRHZ_SHIFT 2 @@ -164,7 +164,7 @@ /* GPCM Timeout Count */ #define CSOR_GPCM_GPTO_MASK 0x0F000000 #define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) /* GPCM External Access Termination mode for read access */ #define CSOR_GPCM_RGETA_EXT 0x00080000 /* GPCM External Access Termination mode for write access */ @@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes { */ #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) +#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) /* * NAND_AUTOBOOT_TRGR @@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes { /* Sequence Timeout Count */ #define IFC_NORCR_STOCNT_MASK 0x000F0000 #define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) +#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) /* * GPCM Machine specific registers |