diff options
| -rw-r--r-- | arch/mips/lib/cache.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 91b037f87d..eba7fff316 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -10,6 +10,7 @@ #ifdef CONFIG_MIPS_L2_CACHE #include <asm/cm.h> #endif +#include <asm/io.h> #include <asm/mipsregs.h> DECLARE_GLOBAL_DATA_PTR; @@ -116,7 +117,7 @@ void flush_cache(ulong start_addr, ulong size) /* flush I-cache & D-cache simultaneously */ cache_loop(start_addr, start_addr + size, ilsize, HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); - return; + goto ops_done; } /* flush D-cache */ @@ -129,6 +130,10 @@ void flush_cache(ulong start_addr, ulong size) /* flush I-cache */ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); + +ops_done: + /* ensure cache ops complete before any further memory accesses */ + sync(); } void flush_dcache_range(ulong start_addr, ulong stop) @@ -145,6 +150,9 @@ void flush_dcache_range(ulong start_addr, ulong stop) /* flush L2 cache */ if (slsize) cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); + + /* ensure cache ops complete before any further memory accesses */ + sync(); } void invalidate_dcache_range(ulong start_addr, ulong stop) @@ -161,4 +169,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); + + /* ensure cache ops complete before any further memory accesses */ + sync(); } |