diff options
| -rw-r--r-- | arch/arc/lib/libgcc2.c | 75 | ||||
| -rw-r--r-- | board/synopsys/emsdp/config.mk | 2 | ||||
| -rw-r--r-- | board/synopsys/emsdp/emsdp.c | 37 | ||||
| -rw-r--r-- | configs/emsdp_defconfig | 1 |
4 files changed, 115 insertions, 0 deletions
diff --git a/arch/arc/lib/libgcc2.c b/arch/arc/lib/libgcc2.c index b92a841a37..ab1dbe1c13 100644 --- a/arch/arc/lib/libgcc2.c +++ b/arch/arc/lib/libgcc2.c @@ -158,3 +158,78 @@ __umodsi3(long a, long b) { return udivmodsi4(a, b, 1); } + +UDWtype +__udivmoddi4(UDWtype n, UDWtype d, UDWtype *rp) +{ + UDWtype q = 0, r = n, y = d; + UWtype lz1, lz2, i, k; + + /* + * Implements align divisor shift dividend method. This algorithm + * aligns the divisor under the dividend and then perform number of + * test-subtract iterations which shift the dividend left. Number of + * iterations is k + 1 where k is the number of bit positions the + * divisor must be shifted left to align it under the dividend. + * quotient bits can be saved in the rightmost positions of the + * dividend as it shifts left on each test-subtract iteration. + */ + + if (y <= r) { + lz1 = __builtin_clzll(d); + lz2 = __builtin_clzll(n); + + k = lz1 - lz2; + y = (y << k); + + /* + * Dividend can exceed 2 ^ (width - 1) - 1 but still be less + * than the aligned divisor. Normal iteration can drops the + * high order bit of the dividend. Therefore, first + * test-subtract iteration is a special case, saving its + * quotient bit in a separate location and not shifting + * the dividend. + */ + + if (r >= y) { + r = r - y; + q = (1ULL << k); + } + + if (k > 0) { + y = y >> 1; + + /* + * k additional iterations where k regular test + * subtract shift dividend iterations are done. + */ + i = k; + do { + if (r >= y) + r = ((r - y) << 1) + 1; + else + r = (r << 1); + i = i - 1; + } while (i != 0); + + /* + * First quotient bit is combined with the quotient + * bits resulting from the k regular iterations. + */ + q = q + r; + r = r >> k; + q = q - (r << k); + } + } + + if (rp) + *rp = r; + + return q; +} + +UDWtype +__udivdi3(UDWtype n, UDWtype d) +{ + return __udivmoddi4(n, d, (UDWtype *)0); +} diff --git a/board/synopsys/emsdp/config.mk b/board/synopsys/emsdp/config.mk new file mode 100644 index 0000000000..67fd7bf82a --- /dev/null +++ b/board/synopsys/emsdp/config.mk @@ -0,0 +1,2 @@ +PLATFORM_CPPFLAGS += -mlittle-endian -mnorm -mswap -mmpy-option=3 \ + -mbarrel-shifter -mfpu=fpuda_all -mcode-density diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c index c0770b58c1..7a3fd5b7f2 100644 --- a/board/synopsys/emsdp/emsdp.c +++ b/board/synopsys/emsdp/emsdp.c @@ -48,6 +48,43 @@ int mach_cpu_init(void) return 0; } +int board_early_init_r(void) +{ +#define EMSDP_PSRAM_BASE 0xf2001000 +#define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10) +#define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14) +#define CRE_ENABLE BIT(31) +#define CRE_DRIVE_CMD BIT(6) + +#define PSRAM_RCR_DPD BIT(1) +#define PSRAM_RCR_PAGE_MODE BIT(7) + +/* + * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash, + * thus "<< 1". + */ +#define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1) + + // Switch PSRAM controller to command mode + writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0); + // Program Refresh Configuration Register (RCR) for BANK0 + writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP)); + // Switch PSRAM controller back to memory mode + writel(0, PSRAM_FLASH_CONFIG_REG_0); + + + // Switch PSRAM controller to command mode + writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1); + // Program Refresh Configuration Register (RCR) for BANK1 + writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP)); + // Switch PSRAM controller back to memory mode + writel(0, PSRAM_FLASH_CONFIG_REG_1); + + printf("PSRAM initialized.\n"); + + return 0; +} + int board_mmc_init(bd_t *bis) { struct dwmci_host *host = NULL; diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig index 64281d0529..5e55e3e2b2 100644 --- a/configs/emsdp_defconfig +++ b/configs/emsdp_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_SIZE=0x1000 CONFIG_SYS_CLK_FREQ=40000000 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="emsdp# " # CONFIG_CMD_BOOTD is not set |