diff options
| -rw-r--r-- | board/freescale/mpc8360emds/mpc8360emds.c | 39 | ||||
| -rw-r--r-- | include/configs/MPC8360EMDS.h | 25 |
2 files changed, 38 insertions, 26 deletions
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index fc0a0e515e..b5cf7148ee 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -120,7 +120,7 @@ int board_early_init_r(void) extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -void sdram_init(void); +static int sdram_init(unsigned int base); phys_size_t initdram(int board_type) { @@ -147,7 +147,7 @@ phys_size_t initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - sdram_init(); + msize += sdram_init(msize * 1024 * 1024); /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); @@ -219,23 +219,32 @@ int checkboard(void) /* * if MPC8360EMDS is soldered with SDRAM */ -#if defined(CONFIG_SYS_BR2_PRELIM) \ - && defined(CONFIG_SYS_OR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWAR2_PRELIM) +#ifdef CONFIG_SYS_LB_SDRAM /* * Initialize SDRAM memory on the Local Bus. */ -void sdram_init(void) +static int sdram_init(unsigned int base) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; - uint *sdram_addr = (uint *) CONFIG_SYS_LBC_SDRAM_BASE; + const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; + int rem = base % sdram_size; + uint *sdram_addr; + /* window base address should be aligned to the window size */ + if (rem) + base = base - rem + sdram_size; + + sdram_addr = (uint *)base; /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c + * Setup SDRAM Base and Option Registers */ + immap->lbus.bank[2].br = base | CONFIG_SYS_BR2; + immap->lbus.bank[2].or = CONFIG_SYS_OR2; + immap->sysconf.lblaw[2].bar = base; + immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; + /*setup mtrpt, lsrt and lbcr for LB bus */ lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; @@ -284,11 +293,17 @@ void sdram_init(void) asm("sync"); *sdram_addr = 0xff; udelay(100); + + /* + * In non-aligned case we don't [normally] use that memory because + * there is a hole. + */ + if (rem) + return 0; + return CONFIG_SYS_LBC_SDRAM_SIZE; } #else -void sdram_init(void) -{ -} +static int sdram_init(unsigned int base) { return 0; } #endif #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index ee5164ae5f..fbd2457aaf 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -100,6 +100,7 @@ */ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */ #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -231,29 +232,25 @@ #define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ #ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ +#define CONFIG_SYS_LBLAWBAR2 0 +#define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */ /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ /* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * Base address = BR[0:16] = dynamic * port size = 32-bits = BR2[19:20] = 11 * no parity checking = BR2[21:22] = 00 * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * the top 17 bits of BR2. + * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 */ -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ +#define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */ /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -269,7 +266,7 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 +#define CONFIG_SYS_OR2 0xfc006901 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ @@ -518,7 +515,7 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ -/* DDR: cache cacheable */ +/* DDR/LBC SDRAM: cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L @@ -545,9 +542,9 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -/* Local bus SDRAM: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +/* DDR/LBC SDRAM next 256M: cacheable */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |