diff options
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/clock.c | 72 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/clock.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/crm_regs.h | 3 |
3 files changed, 80 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 933ce05b76..e92f10623a 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -50,6 +50,78 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; +void set_usboh3_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1) & + ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + writel(reg, &mxc_ccm->cscmr1); + + reg = readl(&mxc_ccm->cscdr1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + + writel(reg, &mxc_ccm->cscdr1); +} + +void enable_usboh3_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR2); + if (enable) + reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET); + writel(reg, &mxc_ccm->CCGR2); +} + +void set_usb_phy1_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, &mxc_ccm->cscmr1); +} + +void enable_usb_phy1_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET); + writel(reg, &mxc_ccm->CCGR4); +} + +void set_usb_phy2_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, &mxc_ccm->cscmr1); +} + +void enable_usb_phy2_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET); + writel(reg, &mxc_ccm->CCGR4); +} + /* * Calculate the frequency of PLLn. */ diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 1f8a537a56..ea972a3985 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -40,4 +40,9 @@ u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +void set_usb_phy2_clk(void); +void enable_usb_phy2_clk(unsigned char enable); +void set_usboh3_clk(void); +void enable_usboh3_clk(unsigned char enable); + #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index fcc0e36fa5..bdeafbc0df 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -195,7 +195,10 @@ struct mxc_ccm_reg { /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 +#define MXC_CCM_CCGR4_CG5_OFFSET 10 +#define MXC_CCM_CCGR4_CG6_OFFSET 12 #define MXC_CCM_CCGR5_CG5_OFFSET 10 +#define MXC_CCM_CCGR2_CG14_OFFSET 28 /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) |