diff options
53 files changed, 501 insertions, 1207 deletions
diff --git a/board/armltd/integratorap/split_by_variant.sh b/board/armltd/integratorap/split_by_variant.sh index 51dc53f1bd..2c9fe2e519 100755 --- a/board/armltd/integratorap/split_by_variant.sh +++ b/board/armltd/integratorap/split_by_variant.sh @@ -84,8 +84,8 @@ else esac fi -if [ "$cpu" = "arm_intcm" ] -then +case "$cpu" in + arm_intcm) echo "/* Core module undefined/not ported */" >> tmp.fil echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil @@ -102,7 +102,19 @@ then echo "initialization reg */" >> tmp.fil echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil echo " /* CM may not have TCRAM */" >> tmp.fil -fi + echo -n " /* May not be processor " >> tmp.fil + echo "without cache support */" >> tmp.fil + echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil + echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil + ;; + + arm720t) + echo -n " /* May not be processor " >> tmp.fil + echo "without cache support */" >> tmp.fil + echo "#define CONFIG_SYS_NO_ICACHE 1" >> tmp.fil + echo "#define CONFIG_SYS_NO_DCACHE 1" >> tmp.fil + ;; +esac mkdir -p ${obj}include mkdir -p ${obj}board/armltd/integratorap diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c index 8d6065196f..cc8e2f9a48 100644 --- a/board/omap3/beagle/beagle.c +++ b/board/omap3/beagle/beagle.c @@ -38,10 +38,10 @@ static int beagle_revision_c; -/****************************************************************************** +/* * Routine: board_init * Description: Early hardware init. - *****************************************************************************/ + */ int board_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -55,23 +55,23 @@ int board_init(void) return 0; } -/****************************************************************************** +/* * Routine: beagle_get_revision * Description: Return revision of the BeagleBoard this code is running on. * If it is a revision Ax/Bx board, this function returns 0, * on a revision C board you will get a 1. - *****************************************************************************/ + */ int beagle_get_revision(void) { return beagle_revision_c; } -/****************************************************************************** +/* * Routine: beagle_identify * Description: Detect if we are running on a Beagle revision Ax/Bx or * Cx. This can be done by GPIO_171. If this is low, we are * running on a revision C board. - *****************************************************************************/ + */ void beagle_identify(void) { gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; @@ -92,10 +92,10 @@ void beagle_identify(void) } } -/****************************************************************************** +/* * Routine: misc_init_r * Description: Configure board specific parts - *****************************************************************************/ + */ int misc_init_r(void) { gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; @@ -121,12 +121,12 @@ int misc_init_r(void) return 0; } -/****************************************************************************** +/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary * mode. - *****************************************************************************/ + */ void set_muxconf_regs(void) { MUX_BEAGLE(); diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index 3a27c8fe5d..c008c2e4aa 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -36,10 +36,10 @@ #include <asm/mach-types.h> #include "evm.h" -/****************************************************************************** +/* * Routine: board_init * Description: Early hardware init. - *****************************************************************************/ + */ int board_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -53,10 +53,10 @@ int board_init(void) return 0; } -/****************************************************************************** +/* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) - *****************************************************************************/ + */ int misc_init_r(void) { @@ -73,22 +73,22 @@ int misc_init_r(void) return 0; } -/****************************************************************************** +/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary * mode. - *****************************************************************************/ + */ void set_muxconf_regs(void) { MUX_EVM(); } -/****************************************************************************** +/* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the * Ethernet hardware. - *****************************************************************************/ + */ static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; diff --git a/board/omap3/overo/overo.c b/board/omap3/overo/overo.c index 37bf350e4e..809b77b642 100644 --- a/board/omap3/overo/overo.c +++ b/board/omap3/overo/overo.c @@ -35,10 +35,10 @@ #include <asm/mach-types.h> #include "overo.h" -/****************************************************************************** +/* * Routine: board_init * Description: Early hardware init. - *****************************************************************************/ + */ int board_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -52,10 +52,10 @@ int board_init(void) return 0; } -/****************************************************************************** +/* * Routine: misc_init_r * Description: Configure board specific parts - *****************************************************************************/ + */ int misc_init_r(void) { power_init_r(); @@ -65,12 +65,12 @@ int misc_init_r(void) return 0; } -/****************************************************************************** +/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary * mode. - *****************************************************************************/ + */ void set_muxconf_regs(void) { MUX_OVERO(); diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h index 71de3f10d3..e8ccc1d2e6 100644 --- a/board/omap3/overo/overo.h +++ b/board/omap3/overo/overo.h @@ -185,6 +185,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\ /*Audio Interface */\ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ @@ -295,7 +296,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ /* - W2W_NRESET*/\ @@ -303,9 +304,9 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT7*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT6*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT5*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ diff --git a/board/omap3/pandora/pandora.c b/board/omap3/pandora/pandora.c index dfd51ecfcb..c2f98ead6a 100644 --- a/board/omap3/pandora/pandora.c +++ b/board/omap3/pandora/pandora.c @@ -36,10 +36,10 @@ #include <asm/mach-types.h> #include "pandora.h" -/****************************************************************************** +/* * Routine: board_init * Description: Early hardware init. - *****************************************************************************/ + */ int board_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -53,10 +53,10 @@ int board_init(void) return 0; } -/****************************************************************************** +/* * Routine: misc_init_r * Description: Configure board specific parts - *****************************************************************************/ + */ int misc_init_r(void) { gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE; @@ -82,12 +82,12 @@ int misc_init_r(void) return 0; } -/****************************************************************************** +/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary * mode. - *****************************************************************************/ + */ void set_muxconf_regs(void) { MUX_PANDORA(); diff --git a/board/omap3/zoom1/zoom1.c b/board/omap3/zoom1/zoom1.c index 702f732753..db4d08709f 100644 --- a/board/omap3/zoom1/zoom1.c +++ b/board/omap3/zoom1/zoom1.c @@ -37,10 +37,10 @@ #include <asm/mach-types.h> #include "zoom1.h" -/****************************************************************************** +/* * Routine: board_init * Description: Early hardware init. - *****************************************************************************/ + */ int board_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -54,10 +54,10 @@ int board_init(void) return 0; } -/****************************************************************************** +/* * Routine: misc_init_r * Description: Configure zoom board specific configurations - *****************************************************************************/ + */ int misc_init_r(void) { power_init_r(); @@ -65,12 +65,12 @@ int misc_init_r(void) return 0; } -/****************************************************************************** +/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary * mode. - *****************************************************************************/ + */ void set_muxconf_regs(void) { /* platform specific muxes */ diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index e0119a771c..47f72f6132 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -104,6 +104,13 @@ lowlevel_init: bl nand_asm_init #endif + /* Memory subsystem address 0x7e00f120 */ + ldr r0, =ELFIN_MEM_SYS_CFG + + /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ + mov r1, #S3C64XX_MEM_SYS_CFG_NAND + str r1, [r0] + bl mem_ctrl_asm_init /* Wakeup support. Don't know if it's going to be used, untested. */ diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 04861632e1..e03a765434 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -33,55 +33,13 @@ #include <common.h> #include <command.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ +static void cache_flush(void); int cpu_init (void) { @@ -104,8 +62,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); #ifdef CONFIG_LCD @@ -119,44 +75,18 @@ int cleanup_before_linux (void) #endif /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ - return(0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return(0); -} - -void icache_enable (void) -{ - ulong reg; + cache_flush(); - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + return 0; } -void icache_disable (void) +static void cache_flush(void) { - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} + unsigned long i = 0; -int icache_status (void) -{ - return(read_p15_c1 () & C1_IC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ } diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 1e94f7d6d0..bfa437835c 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -34,55 +34,10 @@ #include <common.h> #include <command.h> #include <s3c6400.h> +#include <asm/system.h> static void cache_flush (void); -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++) - __asm__ __volatile__("nop\n"); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1 << 0) /* mmu off/on */ -#define C1_ALIGN (1 << 1) /* alignment faults off/on */ -#define C1_DC (1 << 2) /* dcache off/on */ -#define C1_WB (1 << 3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1 << 7) /* big endian off/on */ -#define C1_SYS_PROT (1 << 8) /* system protection */ -#define C1_ROM_PROT (1 << 9) /* ROM protection */ -#define C1_IC (1 << 12) /* icache off/on */ -#define C1_HIGH_VECTORS (1 << 13) /* location of vectors: low/high */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - int cpu_init (void) { return 0; @@ -102,6 +57,7 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable(); + /* flush I/D-cache */ cache_flush(); return 0; @@ -123,61 +79,6 @@ void reset_cpu (ulong ignored) /*NOTREACHED*/ } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return 0; -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_DC); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; -} - /* flush I/D-cache */ static void cache_flush (void) { diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/cpu/arm1176/s3c64xx/cpu_init.S index 08bda99fdc..32bb467f2f 100644 --- a/cpu/arm1176/s3c64xx/cpu_init.S +++ b/cpu/arm1176/s3c64xx/cpu_init.S @@ -28,13 +28,6 @@ .globl mem_ctrl_asm_init mem_ctrl_asm_init: - /* Memory subsystem address 0x7e00f120 */ - ldr r0, =ELFIN_MEM_SYS_CFG - - /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ - mov r1, #0xd - str r1, [r0] - /* DMC1 base address 0x7e001000 */ ldr r0, =ELFIN_DMC1_BASE diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 8166982e6a..6c40903b7d 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -34,6 +34,11 @@ #include <command.h> #include <clps7111.h> #include <asm/hardware.h> +#include <asm/system.h> + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) +static void cache_flush(void); +#endif int cpu_init (void) { @@ -58,17 +63,14 @@ int cleanup_before_linux (void) */ #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; @@ -84,109 +86,13 @@ int cleanup_before_linux (void) return 0; } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* - * Instruction and Data cache enable and disable functions - * - */ - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - /* printf("p15/c1 is = %08lx\n", value); */ - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - /* printf("write %08lx to p15/c1\n", value); */ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_IDC (1<<2) /* icache and/or dcache off/on */ -#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IDC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IDC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IDC) != 0; -} - -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IDC); -} - -void dcache_disable (void) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IDC); -} + unsigned long i = 0; -int dcache_status (void) -{ - return (read_p15_c1 () & C1_IDC) != 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 1b9cde62fa..87c1adc591 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm920t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM920T Technical reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - +static void cache_flush(void); int cpu_init (void) { @@ -110,76 +61,21 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + cache_flush(); - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); + return 0; } -void dcache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0; - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -#endif diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c index b9f09318ad..cf6a489101 100644 --- a/cpu/arm925t/cpu.c +++ b/cpu/arm925t/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm925t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ +static void cache_flush(void); int cpu_init (void) { @@ -110,48 +61,23 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + return 0; } -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0; - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 48a2c0bf21..6307e3389d 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm926ejs.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM926EJ-S Technical Reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - +static void cache_flush(void); int cpu_init (void) { @@ -110,76 +61,22 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* cache_bit must be either C1_IC or C1_DC */ -static void cache_enable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = read_p15_c1(); /* get control reg. */ - cp_delay(); - write_p15_c1(reg | cache_bit); -} - -/* cache_bit must be either C1_IC or C1_DC */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = read_p15_c1(); - cp_delay(); - write_p15_c1(reg & ~cache_bit); -} - -void icache_enable(void) -{ - cache_enable(C1_IC); -} - -void icache_disable(void) -{ - cache_disable(C1_IC); -} - -int icache_status(void) -{ - return (read_p15_c1() & C1_IC) != 0; -} - -void dcache_enable(void) -{ - cache_enable(C1_DC); + return 0; } -void dcache_disable(void) +/* flush I/D-cache */ +static void cache_flush (void) { - cache_disable(C1_DC); -} + unsigned long i = 0; -int dcache_status(void) -{ - return (read_p15_c1() & C1_DC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index 44c589aef9..ef7995d609 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm946es.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM946E-S Technical Reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - +static void cache_flush(void); int cpu_init (void) { @@ -110,8 +61,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); /* ARM926E-S needs the protection unit enabled for the icache to have @@ -119,47 +68,19 @@ int cleanup_before_linux (void) * should turn off the protection unit as well.... */ /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} -/* ARM926E-S needs the protection unit enabled for this to have any effect - - left for possible later use */ -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + return 0; } -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} + unsigned long i = 0; -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index ad2085b010..5e7b935e4b 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -34,6 +34,7 @@ #include <common.h> #include <command.h> #include <asm/arch/sys_proto.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -45,46 +46,6 @@ void l2cache_disable(void); static void cache_flush(void); -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\ - @ read control reg\n":"=r"(value) - ::"memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\ - @ write it back\n"::"r"(value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay(void) -{ - /* Many OMAP regs need at least 2 nops */ - asm("nop"); - asm("nop"); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - int cpu_init(void) { /* @@ -134,42 +95,6 @@ int cleanup_before_linux(void) return 0; } -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts(); - reset_cpu(0); - - /* NOTREACHED */ - return 0; -} - -void icache_enable(void) -{ - ulong reg; - - reg = read_p15_c1(); /* get control reg. */ - cp_delay(); - write_p15_c1(reg | C1_IC); -} - -void icache_disable(void) -{ - ulong reg; - - reg = read_p15_c1(); - cp_delay(); - write_p15_c1(reg & ~C1_IC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_DC); -} - void l2cache_enable() { unsigned long i; @@ -229,11 +154,6 @@ void l2cache_disable() } } -int icache_status(void) -{ - return (read_p15_c1() & C1_IC) != 0; -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 7bb3e284b5..15ea936b40 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -331,7 +331,7 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; usage: - printf ("Usage: nandecc %s\n", cmdtp->help); + printf ("Usage: nandecc %s\n", cmdtp->usage); return 1; } diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c index ccf7fd5b64..1636ffb1ff 100644 --- a/cpu/arm_intcm/cpu.c +++ b/cpu/arm_intcm/cpu.c @@ -66,28 +66,3 @@ int cleanup_before_linux (void) return (0); } - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* May not be cahed processor on the CM - do nothing */ -void icache_enable (void) -{ -} - -void icache_disable (void) -{ -} - -/* return "disabled" */ -int icache_status (void) -{ - return 0; -} diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index fd545b5a25..42c62f6e39 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -34,6 +34,7 @@ #include <command.h> #include <netdev.h> #include <asm/arch/ixp425.h> +#include <asm/system.h> ulong loops_per_jiffy; @@ -41,6 +42,8 @@ ulong loops_per_jiffy; DECLARE_GLOBAL_DATA_PTR; #endif +static void cache_flush(void); + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { @@ -98,92 +101,26 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */ - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); + cache_flush(); - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + return 0; } -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* clear i-cache */ - i &= ~0x1000; + unsigned long i = 0; - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - /* FIXME */ /* void pci_init(void) diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index 8ff3a36821..93ebd13234 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -32,61 +32,13 @@ #include <common.h> #include <command.h> #include <arm920t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ +static void cache_flush(void); int cpu_init (void) { @@ -109,75 +61,22 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); + return 0; } -void dcache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0; - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -#endif diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index e84cb5b156..3a1be57f44 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -33,11 +33,14 @@ #include <common.h> #include <command.h> #include <asm/arch/pxa-regs.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif +static void cache_flush(void); + int cpu_init (void) { /* @@ -59,92 +62,26 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */ - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); return (0); } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +/* flush I/D-cache */ +static void cache_flush (void) { - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + unsigned long i = 0; - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - #ifndef CONFIG_CPU_MONAHANS void set_GPIO_mode(int gpio_mode) { diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index e4cdb823b4..7ef4a1fdb0 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -72,12 +72,3 @@ void reset_cpu (ulong addr) /*NOP*/ } } - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c index bb4e5a1de9..ed1a6f7cd3 100644 --- a/cpu/sa1100/cpu.c +++ b/cpu/sa1100/cpu.c @@ -32,11 +32,14 @@ #include <common.h> #include <command.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif +static void cache_flush(void); + int cpu_init (void) { /* @@ -58,88 +61,22 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */ - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); return (0); } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +/* flush I/D-cache */ +static void cache_flush (void) { - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + unsigned long i = 0; - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } - -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h new file mode 100644 index 0000000000..2b28a261ba --- /dev/null +++ b/include/asm-arm/system.h @@ -0,0 +1,84 @@ +#ifndef __ASM_ARM_SYSTEM_H +#define __ASM_ARM_SYSTEM_H + +#ifdef __KERNEL__ + +#define CPU_ARCH_UNKNOWN 0 +#define CPU_ARCH_ARMv3 1 +#define CPU_ARCH_ARMv4 2 +#define CPU_ARCH_ARMv4T 3 +#define CPU_ARCH_ARMv5 4 +#define CPU_ARCH_ARMv5T 5 +#define CPU_ARCH_ARMv5TE 6 +#define CPU_ARCH_ARMv5TEJ 7 +#define CPU_ARCH_ARMv6 8 +#define CPU_ARCH_ARMv7 9 + +/* + * CR1 bits (CP#15 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_W (1 << 3) /* Write buffer enable */ +#define CR_P (1 << 4) /* 32-bit exception handler */ +#define CR_D (1 << 5) /* 32-bit data address range */ +#define CR_L (1 << 6) /* Implementation defined */ +#define CR_B (1 << 7) /* Big endian */ +#define CR_S (1 << 8) /* System MMU protection */ +#define CR_R (1 << 9) /* ROM MMU protection */ +#define CR_F (1 << 10) /* Implementation defined */ +#define CR_Z (1 << 11) /* Implementation defined */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR (1 << 14) /* Round Robin cache replacement */ +#define CR_L4 (1 << 15) /* LDR pc can set T bit */ +#define CR_DT (1 << 16) +#define CR_IT (1 << 18) +#define CR_ST (1 << 19) +#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ +#define CR_U (1 << 22) /* Unaligned access operation */ +#define CR_XP (1 << 23) /* Extended page tables */ +#define CR_VE (1 << 24) /* Vectored interrupts */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ +#define CR_TRE (1 << 28) /* TEX remap enable */ +#define CR_AFE (1 << 29) /* Access flag enable */ +#define CR_TE (1 << 30) /* Thumb exception enable */ + +/* + * This is used to ensure the compiler did actually allocate the register we + * asked it for some inline assembly sequences. Apparently we can't trust + * the compiler from one version to another so a bit of paranoia won't hurt. + * This string is meant to be concatenated with the inline asm string and + * will cause compilation to stop on mismatch. + * (for details, see gcc PR 15089) + */ +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +#ifndef __ASSEMBLY__ + +#define isb() __asm__ __volatile__ ("" : : : "memory") + +#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); + +static inline unsigned int get_cr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_cr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" + : : "r" (val) : "cc"); + isb(); +} + +#endif /* __ASSEMBLY__ */ + +#define arch_align_stack(x) (x) + +#endif /* __KERNEL__ */ + +#endif diff --git a/include/configs/B2.h b/include/configs/B2.h index 01b65c515d..35fad5c553 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -38,6 +38,7 @@ #define CONFIG_B2 1 /* on an B2 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#define CONFIG_SYS_NO_CP15_CACHE #define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ diff --git a/include/configs/assabet.h b/include/configs/assabet.h index a6c442b51a..8c5b84cf69 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -37,6 +37,8 @@ #define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ #undef CONFIG_USE_IRQ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 751e03c13f..82d1401469 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -41,6 +41,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 850d93b03e..75c5f9bb3e 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -37,6 +37,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index d9f85f01ee..ed1845009e 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -42,6 +42,10 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Hardware drivers */ diff --git a/include/configs/delta.h b/include/configs/delta.h index f5508b7740..bacbd90b5d 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -39,6 +39,9 @@ #undef CONFIG_SKIP_RELOCATE_UBOOT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index 8f615bdb84..b6cfc6721d 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -42,6 +42,8 @@ #define CONFIG_DNP1110 1 /* on an DNP/1110 Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE /* * Size of malloc() pool diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index ffc9408bc8..0f415d9c8b 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -43,6 +43,7 @@ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */ #define CONFIG_EVB4510 1 /* on an EVB4510 Board */ +#define CONFIG_SYS_NO_CP15_CACHE #define CONFIG_USE_IRQ #define CONFIG_STACKSIZE_IRQ (4*1024) diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index 77d45783c3..b2fbca2f3c 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -49,6 +49,8 @@ #define CONFIG_GCPLUS 1 /* on an ADS GCPlus Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 895998adf4..69654c7c0f 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -39,6 +39,10 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Hardware drivers */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 9231e64039..38c024953e 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -142,7 +142,7 @@ * PCI definitions */ -/*#define CONFIG_PCI /--* include pci support */ +#ifdef CONFIG_PCI /* pci support */ #undef CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define DEBUG @@ -150,7 +150,6 @@ #define CONFIG_EEPRO100 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 @@ -278,6 +277,7 @@ #define INTEGRATOR_SC_PCIENABLE \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) +#endif /* CONFIG_PCI */ /*----------------------------------------------------------------------- * There are various dependencies on the core module (CM) fitted * Users should refer to their CM user guide diff --git a/include/configs/lart.h b/include/configs/lart.h index e34ec222b8..5d6d460424 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -35,6 +35,8 @@ #define CONFIG_LART 1 /* on an LART Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE /* * Size of malloc() pool diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 9afa800139..889a9a344d 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -39,6 +39,10 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* for timer/console/ethernet */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Hardware drivers */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index a4b430bbc5..2cf9c02815 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -46,6 +46,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c60778c0f0..8e984b4161 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -303,21 +303,4 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif - -#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, &nand_cs_base->nand_cmd) -#define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, &nand_cs_base->nand_adr) -#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) -#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) - -/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ - while (0) -#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ - while (0) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) udelay(10) - #endif /* __CONFIG_H */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index ab9ea4fdee..ed873faca7 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -42,6 +42,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 5e2e7cfcc8..7485f7241c 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -68,6 +68,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h index c8b0b161d8..13cc5ff3b7 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -44,6 +44,8 @@ #define CONFIG_SHANNON 1 /* on an SHANNON/TuxScreen Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE /* * Size of malloc() pool diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index c2744b5eba..49173181fb 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -47,6 +47,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + #define RTC /* diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index e74303da85..197ac0bbd6 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -27,6 +27,8 @@ #define CONFIG_WEPEP250 1 /* config for wepep250 board */ #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE /* * Select serial console configuration diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 086ca69c10..1632d29622 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -49,6 +49,9 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * select serial console configuration */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 922eb2c6b0..c8bdf3186b 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -36,6 +36,9 @@ #define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool; this lives below the uppermost 128 KiB which are * used for the RAM copy of the uboot code diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index cad414c1d9..7e2abbf346 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -35,6 +35,9 @@ #define CONFIG_DOS_PARTITION 1 #define BOARD_LATE_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 064740d3cc..217636a618 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -47,6 +47,9 @@ #undef CONFIG_SKIP_RELOCATE_UBOOT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + /* * Size of malloc() pool */ diff --git a/include/s3c6400.h b/include/s3c6400.h index fd3e99bcfa..87f3760b6c 100644 --- a/include/s3c6400.h +++ b/include/s3c6400.h @@ -215,9 +215,9 @@ #define GPACONSLP_OFFSET 0x0C #define GPAPUDSLP_OFFSET 0x10 #define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x04 -#define GPBPUD_OFFSET 0x08 -#define GPBCONSLP_OFFSET 0x0C +#define GPBDAT_OFFSET 0x24 +#define GPBPUD_OFFSET 0x28 +#define GPBCONSLP_OFFSET 0x2C #define GPBPUDSLP_OFFSET 0x30 #define GPCCON_OFFSET 0x40 #define GPCDAT_OFFSET 0x44 @@ -380,6 +380,11 @@ */ #define ELFIN_MEM_SYS_CFG 0x7e00f120 +#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) + +#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 +#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT + #define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) #define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) #define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) diff --git a/lib_arm/Makefile b/lib_arm/Makefile index c8795b2314..4469361a8a 100644 --- a/lib_arm/Makefile +++ b/lib_arm/Makefile @@ -35,8 +35,12 @@ SOBJS-y += _umodsi3.o COBJS-y += board.o COBJS-y += bootm.o COBJS-y += cache.o +ifndef CONFIG_SYS_NO_CP15_CACHE +COBJS-y += cache-cp15.o +endif COBJS-y += div0.o COBJS-y += interrupts.o +COBJS-y += reset.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/lib_arm/cache-cp15.c b/lib_arm/cache-cp15.c new file mode 100644 index 0000000000..62ed54fb4d --- /dev/null +++ b/lib_arm/cache-cp15.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/system.h> + +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) +static void cp_delay (void) +{ + volatile int i; + + /* copro seems to need some delay between reading and writing */ + for (i = 0; i < 100; i++) + nop(); +} + +/* cache_bit must be either CR_I or CR_C */ +static void cache_enable(uint32_t cache_bit) +{ + uint32_t reg; + + reg = get_cr(); /* get control reg. */ + cp_delay(); + set_cr(reg | cache_bit); +} + +/* cache_bit must be either CR_I or CR_C */ +static void cache_disable(uint32_t cache_bit) +{ + uint32_t reg; + + reg = get_cr(); + cp_delay(); + set_cr(reg & ~cache_bit); +} +#endif + +#ifdef CONFIG_SYS_NO_ICACHE +void icache_enable (void) +{ + return; +} + +void icache_disable (void) +{ + return; +} + +int icache_status (void) +{ + return 0; /* always off */ +} +#else +void icache_enable(void) +{ + cache_enable(CR_I); +} + +void icache_disable(void) +{ + cache_disable(CR_I); +} + +int icache_status(void) +{ + return (get_cr() & CR_I) != 0; +} +#endif + +#ifdef CONFIG_SYS_NO_DCACHE +void dcache_enable (void) +{ + return; +} + +void dcache_disable (void) +{ + return; +} + +int dcache_status (void) +{ + return 0; /* always off */ +} +#else +void dcache_enable(void) +{ + cache_enable(CR_C); +} + +void dcache_disable(void) +{ + cache_disable(CR_C); +} + +int dcache_status(void) +{ + return (get_cr() & CR_C) != 0; +} +#endif diff --git a/lib_arm/reset.c b/lib_arm/reset.c new file mode 100644 index 0000000000..550d1e59c7 --- /dev/null +++ b/lib_arm/reset.c @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * (C) Copyright 2004 Texas Insturments + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + puts ("resetting ...\n"); + + udelay (50000); /* wait 50 ms */ + + disable_interrupts(); + reset_cpu(0); + + /*NOTREACHED*/ + return 0; +} |