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-rw-r--r--arch/arm/mach-mvebu/armada8k/cpu.c24
-rw-r--r--include/configs/mvebu_armada-8k.h3
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index f8e8e73610..959a7cff76 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -18,6 +18,10 @@
#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
#define RFU_SW_RESET_OFFSET 0
+#define SAR0_REG (MVEBU_REGISTER(0x2400200))
+#define BOOT_MODE_MASK 0x3f
+#define BOOT_MODE_OFFSET 4
+
/*
* The following table includes all memory regions for Armada 7k and
* 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
@@ -125,3 +129,23 @@ u32 mvebu_get_nand_clock(void)
else
return 250 * 1000000;
}
+
+int mmc_get_env_dev(void)
+{
+ u32 reg;
+ unsigned int boot_mode;
+
+ reg = readl(SAR0_REG);
+ boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK;
+
+ switch (boot_mode) {
+ case 0x28:
+ case 0x2a:
+ return 0;
+ case 0x29:
+ case 0x2b:
+ return 1;
+ }
+
+ return CONFIG_SYS_MMC_ENV_DEV;
+}
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 93c50488a2..a6636e19e8 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -64,6 +64,9 @@
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+/* When runtime detection fails this is the default */
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_ONFI_DETECTION