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-rw-r--r--arch/arm/dts/stm32f746.dtsi1
-rw-r--r--drivers/spi/stm32_qspi.c16
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index b2b0b5f099..883f818578 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -78,6 +78,7 @@
reg-names = "QuadSPI", "QuadSPI-memory";
interrupts = <92>;
spi-max-frequency = <108000000>;
+ clocks = <&rcc 0 65>;
status = "disabled";
};
usart1: serial@40011000 {
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 05358ebf4c..f0434a4413 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -17,6 +17,7 @@
#include <errno.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_defs.h>
+#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -457,7 +458,20 @@ static int stm32_qspi_probe(struct udevice *bus)
priv->max_hz = plat->max_hz;
- clock_setup(QSPI_CLOCK_CFG);
+#ifdef CONFIG_CLK
+ int ret;
+ struct clk clk;
+ ret = clk_get_by_index(bus, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ dev_err(bus, "failed to enable clock\n");
+ return ret;
+ }
+#endif
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);