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-rw-r--r--CHANGELOG2
-rw-r--r--board/m5271evb/m5271evb.c7
-rw-r--r--board/r5200/r5200.c5
-rw-r--r--cpu/arm926ejs/cpuinfo.c1
-rw-r--r--cpu/mcf52x2/cpu_init.c50
-rw-r--r--cpu/mcf52x2/serial.c2
-rw-r--r--include/configs/MPC8349EMDS.h2
-rw-r--r--include/configs/r5200.h2
-rw-r--r--lib_m68k/board.c2
9 files changed, 36 insertions, 37 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 494d0b0deb..a0b6f0594b 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
+* Minor cleanup.
+
* Update yosemite configuration to enable flash write buffer support
Patch by Stefan Roese, 10 May 2006
diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c
index d364bd612c..c26c91d1b7 100644
--- a/board/m5271evb/m5271evb.c
+++ b/board/m5271evb/m5271evb.c
@@ -53,10 +53,9 @@ long int initdram (int board_type) {
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE))
- {
+ if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
/* Initialize DRAM Control Register: DCR */
- mbar_writeShort(MCF_SDRAMC_DCR,
+ mbar_writeShort(MCF_SDRAMC_DCR,
MCF_SDRAMC_DCR_RTIM(0x01)
| MCF_SDRAMC_DCR_RC(0x30));
@@ -74,7 +73,7 @@ long int initdram (int board_type) {
| MCF_SDRAMC_DACRn_PS(0));
/* Initialize DMR0 */
- mbar_writeLong(MCF_SDRAMC_DMR0,
+ mbar_writeLong(MCF_SDRAMC_DMR0,
MCF_SDRAMC_DMRn_BAM_16M
| MCF_SDRAMC_DMRn_V);
diff --git a/board/r5200/r5200.c b/board/r5200/r5200.c
index e51ad252f3..69f3a765b6 100644
--- a/board/r5200/r5200.c
+++ b/board/r5200/r5200.c
@@ -47,8 +47,7 @@ long int initdram (int board_type) {
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
- if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE))
- {
+ if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
/*
* Initialize DRAM Control Register: DCR
*/
@@ -67,7 +66,7 @@ long int initdram (int board_type) {
/*
* Initialize DMR0
*/
- mbar_writeLong(MCF_SDRAMC_DMR0,
+ mbar_writeLong(MCF_SDRAMC_DMR0,
MCF_SDRAMC_DMRn_BAM_8M
| MCF_SDRAMC_DMRn_V);
diff --git a/cpu/arm926ejs/cpuinfo.c b/cpu/arm926ejs/cpuinfo.c
index 410a2351c6..8c9863161a 100644
--- a/cpu/arm926ejs/cpuinfo.c
+++ b/cpu/arm926ejs/cpuinfo.c
@@ -242,4 +242,3 @@ int print_cpuinfo (void)
}
#endif /* #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP) */
-
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index d33adc2dcb..451e3f3f10 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -58,9 +58,9 @@ void cpu_init_f (void)
/* Enable UART pins */
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
- MCF_GPIO_PAR_UART_U0RXD |
- MCF_GPIO_PAR_UART_U1RXD_UART1 |
- MCF_GPIO_PAR_UART_U1TXD_UART1);
+ MCF_GPIO_PAR_UART_U0RXD |
+ MCF_GPIO_PAR_UART_U1RXD_UART1 |
+ MCF_GPIO_PAR_UART_U1TXD_UART1);
/* Enable Ethernet pins */
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
@@ -69,7 +69,7 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r (void)
{
return (0);
}
@@ -97,7 +97,7 @@ void cpu_init_f (void)
regp->sysctrl_reg.sc_scr = CFG_SCR;
regp->sysctrl_reg.sc_spr = CFG_SPR;
- /* Setup Ports: */
+ /* Setup Ports: */
regp->gpio_reg.gpio_pacnt = CFG_PACNT;
regp->gpio_reg.gpio_paddr = CFG_PADDR;
regp->gpio_reg.gpio_padat = CFG_PADAT;
@@ -147,15 +147,15 @@ void cpu_init_f (void)
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
- /* enable instruction cache now */
- icache_enable();
+ /* enable instruction cache now */
+ icache_enable();
}
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r (void)
{
return (0);
}
@@ -178,7 +178,7 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r (void)
{
return (0);
}
@@ -202,23 +202,23 @@ void cpu_init_f (void)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#ifdef CFG_FAST_CLK
- pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
+ pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
- pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
+ pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
#endif
- cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
- pllcr ^= 0x00000001; /* Set pll bypass to 1 */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
- udelay(0x20); /* Wait for a lock ... */
+ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+ mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
+ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
+ pllcr ^= 0x00000001; /* Set pll bypass to 1 */
+ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
+ udelay(0x20); /* Wait for a lock ... */
#endif /* #ifndef CFG_PLL_BYPASS */
/*
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
- * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
- * which is their primary function.
- * ~Jeremy
+ * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
+ * which is their primary function.
+ * ~Jeremy
*/
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
@@ -233,7 +233,7 @@ void cpu_init_f (void)
* (Internal Register Display) command
* ~Jeremy
*
- */
+ */
mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
@@ -252,9 +252,9 @@ void cpu_init_f (void)
mbar_writeByte(MCFSIM_QSPIICR, 0x00);
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
- mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
+ mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
- mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
+ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
/* Setup interrupt priorities for gpio7 */
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
@@ -282,7 +282,7 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r (void)
{
return (0);
}
diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c
index c66bdef768..10117889ad 100644
--- a/cpu/mcf52x2/serial.c
+++ b/cpu/mcf52x2/serial.c
@@ -106,7 +106,7 @@ void rs_serial_init(int port,int baudrate)
/* Set clock Select Register: Tx/Rx clock is timer */
uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
-
+
rs_serial_setbaudrate(port,baudrate);
/* Enable Tx/Rx */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 0300b0d949..66f164660e 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -39,7 +39,7 @@
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
-#undef CONFIG_PCI
+#undef CONFIG_PCI
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define PCI_66M
diff --git a/include/configs/r5200.h b/include/configs/r5200.h
index 7049704590..e1e406bf9b 100644
--- a/include/configs/r5200.h
+++ b/include/configs/r5200.h
@@ -72,7 +72,7 @@
#include <cmd_confdefs.h>
/* Note: We only copy one sectors worth of application code from location
- * 10200000 for speed purposes. Increase the size if necessary */
+ * 10200000 for speed purposes. Increase the size if necessary */
#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400"
#define CONFIG_BOOTDELAY 1
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 73d2e3f749..6aaf60991c 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -363,7 +363,7 @@ board_init_f (ulong bootflag)
*paddr-- = 0;
*paddr-- = 0;
addr_sp = (ulong)paddr;
-
+
debug ("Stack Pointer at: %08lx\n", addr_sp);
/*
generated by cgit (git 2.34.1) at 2024-12-25 12:56:58 +0000