diff options
| -rw-r--r-- | README | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 1 | ||||
| -rw-r--r-- | board/freescale/t104xrdb/spl.c | 4 | ||||
| -rw-r--r-- | include/configs/T104xRDB.h | 10 |
5 files changed, 20 insertions, 4 deletions
@@ -409,6 +409,10 @@ The following options need to be configured: Enables a workaround for IFC erratum A003399. It is only requred during NOR boot. + CONFIG_A008044_WORKAROUND + Enables a workaround for T1040/T1042 erratum A008044. It is only + requred during NAND boot and valid for Rev 1.0 SoC revision + CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY This is the value to write into CCSR offset 0x18600 diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index fe3eb06324..b134096f90 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -313,7 +313,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005434 puts("Work-around for Erratum A-005434 enabled\n"); #endif - +#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \ + defined(CONFIG_A008044_WORKAROUND) + puts("Work-around for Erratum A-008044 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7860b40884..bcce5a3ab7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -769,6 +769,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 3822a37738..75d9d9c5fa 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -34,12 +34,12 @@ unsigned long get_board_ddr_clk(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, uart_clk; -#ifdef CONFIG_SPL_NAND_BOOT +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) u32 porsr1, pinctl; #endif ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#ifdef CONFIG_SPL_NAND_BOOT +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) /* * There is T1040 SoC issue where NOR, FPGA are inaccessible during * NAND boot because IFC signals > IFC_AD7 are not enabled. diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 216f34f75b..6f41dcec2a 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -13,6 +13,9 @@ #define CONFIG_T104xRDB #define CONFIG_PHYS_64BIT +#define CONFIG_E500 /* BOOKE e500 family */ +#include <asm/config_mpc85xx.h> + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg #ifdef CONFIG_T1040RDB @@ -93,7 +96,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ @@ -386,6 +388,12 @@ #define CONFIG_SYS_RAMBOOT #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A008044 +#if defined(CONFIG_NAND) +#define CONFIG_A008044_WORKAROUND +#endif +#endif + #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R |