summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--arch/riscv/Kconfig5
-rw-r--r--arch/riscv/cpu/start.S25
-rw-r--r--arch/riscv/include/asm/encoding.h6
-rw-r--r--arch/riscv/lib/interrupts.c31
-rw-r--r--board/AndesTech/ax25-ae350/ax25-ae350.c3
-rw-r--r--board/emulation/qemu-riscv/Kconfig3
-rw-r--r--board/emulation/qemu-riscv/MAINTAINERS2
-rw-r--r--configs/qemu-riscv32_smode_defconfig10
-rw-r--r--configs/qemu-riscv64_smode_defconfig11
9 files changed, 75 insertions, 21 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3e0af55e71..732a357a99 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -55,6 +55,11 @@ config RISCV_ISA_C
config RISCV_ISA_A
def_bool y
+config RISCV_SMODE
+ bool "Run in S-Mode"
+ help
+ Enable this option to build U-Boot for RISC-V S-Mode
+
config 32BIT
bool
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 15e1b8199a..64246a4e09 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -38,13 +38,11 @@ _start:
mv s0, a0
mv s1, a1
- li t0, CONFIG_SYS_SDRAM_BASE
- SREG a2, 0(t0)
la t0, trap_entry
- csrw mtvec, t0
+ csrw MODE_PREFIX(tvec), t0
/* mask all interrupts */
- csrw mie, zero
+ csrw MODE_PREFIX(ie), zero
/* Enable cache */
jal icache_enable
@@ -166,7 +164,7 @@ fix_rela_dyn:
*/
la t0, trap_entry
add t0, t0, t6
- csrw mtvec, t0
+ csrw MODE_PREFIX(tvec), t0
clear_bss:
la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
@@ -238,17 +236,24 @@ trap_entry:
SREG x29, 29*REGBYTES(sp)
SREG x30, 30*REGBYTES(sp)
SREG x31, 31*REGBYTES(sp)
- csrr a0, mcause
- csrr a1, mepc
+ csrr a0, MODE_PREFIX(cause)
+ csrr a1, MODE_PREFIX(epc)
mv a2, sp
jal handle_trap
- csrw mepc, a0
+ csrw MODE_PREFIX(epc), a0
+#ifdef CONFIG_RISCV_SMODE
+/*
+ * Remain in S-mode after sret
+ */
+ li t0, SSTATUS_SPP
+#else
/*
* Remain in M-mode after mret
*/
li t0, MSTATUS_MPP
- csrs mstatus, t0
+#endif
+ csrs MODE_PREFIX(status), t0
LREG x1, 1*REGBYTES(sp)
LREG x2, 2*REGBYTES(sp)
LREG x3, 3*REGBYTES(sp)
@@ -281,4 +286,4 @@ trap_entry:
LREG x30, 30*REGBYTES(sp)
LREG x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
- mret
+ MODE_PREFIX(ret)
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index 9ea50ce640..97cf906aa6 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -7,6 +7,12 @@
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
+#ifdef CONFIG_RISCV_SMODE
+#define MODE_PREFIX(__suffix) s##__suffix
+#else
+#define MODE_PREFIX(__suffix) m##__suffix
+#endif
+
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 903a1c4cd5..3aff006977 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -34,17 +34,30 @@ int disable_interrupts(void)
return 0;
}
-ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs)
+ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs)
{
- ulong is_int;
+ ulong is_irq, irq;
- is_int = (mcause & MCAUSE_INT);
- if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
- external_interrupt(0); /* handle_m_ext_interrupt */
- else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
- timer_interrupt(0); /* handle_m_timer_interrupt */
- else
- _exit_trap(mcause, epc, regs);
+ is_irq = (cause & MCAUSE_INT);
+ irq = (cause & ~MCAUSE_INT);
+
+ if (is_irq) {
+ switch (irq) {
+ case IRQ_M_EXT:
+ case IRQ_S_EXT:
+ external_interrupt(0); /* handle external interrupt */
+ break;
+ case IRQ_M_TIMER:
+ case IRQ_S_TIMER:
+ timer_interrupt(0); /* handle timer interrupt */
+ break;
+ default:
+ _exit_trap(cause, epc, regs);
+ break;
+ };
+ } else {
+ _exit_trap(cause, epc, regs);
+ }
return epc;
}
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 5f4ca0f5a7..d343453f22 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -14,6 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
+extern phys_addr_t prior_stage_fdt_address;
/*
* Miscellaneous platform dependent initializations
*/
@@ -66,7 +67,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
void *board_fdt_blob_setup(void)
{
- void **ptr = (void *)CONFIG_SYS_SDRAM_BASE;
+ void **ptr = (void *)&prior_stage_fdt_address;
if (fdt_magic(*ptr) == FDT_MAGIC)
return (void *)*ptr;
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 33ca253432..56bb5337d4 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,7 +13,8 @@ config SYS_CONFIG_NAME
default "qemu-riscv"
config SYS_TEXT_BASE
- default 0x80000000
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS
index 3c6eb4f844..c701c83d77 100644
--- a/board/emulation/qemu-riscv/MAINTAINERS
+++ b/board/emulation/qemu-riscv/MAINTAINERS
@@ -4,4 +4,6 @@ S: Maintained
F: board/emulation/qemu-riscv/
F: include/configs/qemu-riscv.h
F: configs/qemu-riscv32_defconfig
+F: configs/qemu-riscv32_smode_defconfig
F: configs/qemu-riscv64_defconfig
+F: configs/qemu-riscv64_smode_defconfig
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
new file mode 100644
index 0000000000..0a84ec1874
--- /dev/null
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -0,0 +1,10 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
new file mode 100644
index 0000000000..b012443370
--- /dev/null
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y