diff options
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 42 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 25 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 99 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 27 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 |
8 files changed, 200 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index bcf6b48a51..8c1317faea 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -33,3 +33,7 @@ endif ifneq ($(CONFIG_LS1012A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o endif + +ifneq ($(CONFIG_LS1046A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 8eee016f11..f7b949aca2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -3,6 +3,7 @@ SoC overview 1. LS1043A 2. LS2080A 3. LS1012A + 4. LS1046A LS1043A --------- @@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features: - Two WatchDog timers - ARM generic timer - QorIQ platform's trust architecture 2.1 + +LS1046A +-------- +The LS1046A integrated multicore processor combines four ARM Cortex-A72 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1046A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A72 CPUs + - 2 MB unified L2 Cache + - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Two Configurable x4 SerDes + - Two PLLs per four-lane SerDes + - Support for 10G operation + - Ethernet interfaces by FMan + - Up to 2 x XFI supporting 10G interface (MAC 9, 10) + - Up to 1 x QSGMII (MAC 5, 6, 10, 1) + - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) + - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) + - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) + - High-speed peripheral interfaces + - Three PCIe 3.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller (IFC) supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index d0dc58d181..8922197d43 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info) case 3: sys_info->freq_fman[0] = freq_c_pll[0] / 3; break; + case 4: + sys_info->freq_fman[0] = freq_c_pll[0] / 4; + break; + case 5: + sys_info->freq_fman[0] = sys_info->freq_systembus; + break; case 6: sys_info->freq_fman[0] = freq_c_pll[1] / 2; break; @@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info) #ifdef CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK rcw_tmp = in_be32(&gur->rcwsr[15]); - rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; - sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { + case 1: + sys_info->freq_sdhc = freq_c_pll[1]; + break; + case 2: + sys_info->freq_sdhc = freq_c_pll[1] / 2; + break; + case 3: + sys_info->freq_sdhc = freq_c_pll[1] / 3; + break; + case 6: + sys_info->freq_sdhc = freq_c_pll[0] / 2; + break; + default: + printf("Error: Unknown ESDHC clock select!\n"); + break; + } #else sys_info->freq_sdhc = sys_info->freq_systembus; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c new file mode 100644 index 0000000000..1da6b7135f --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -0,0 +1,99 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/immap_lsch2.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} }, + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} }, + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, + SGMII_FM1_DTSEC6} }, + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, + SGMII_FM1_DTSEC6} }, + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} }, + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} }, + {0x5506, {PCIE1, PCIE2, NONE, PCIE3} }, + {0x0506, {NONE, PCIE2, NONE, PCIE3} }, + {0x0559, {NONE, PCIE2, PCIE3, SATA1} }, + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} }, + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 7116f9d0a7..b0ad4b4626 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -209,6 +209,33 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#elif defined(CONFIG_LS1046A) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SNVS_LE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION + +/* SMMU Defintions */ +#define SMMU_BASE 0x09000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 5fd5e87ea8..e2d96a1b78 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -13,6 +13,8 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 1f3340442c..e1b3f44d85 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -151,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 39e8c7a17c..8d4a7adb1d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -44,6 +44,8 @@ struct cpu_type { #define SVR_LS1012A 0x870400 #define SVR_LS1043A 0x879200 #define SVR_LS1023A 0x879208 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 #define SVR_LS2045A 0x870120 #define SVR_LS2080A 0x870110 #define SVR_LS2085A 0x870100 |