diff options
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/Kconfig | 4 | ||||
| -rw-r--r-- | board/esd/du405/Kconfig | 12 | ||||
| -rw-r--r-- | board/esd/du405/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/esd/du405/Makefile | 8 | ||||
| -rw-r--r-- | board/esd/du405/du405.c | 187 | ||||
| -rw-r--r-- | board/esd/du405/du405.h | 28 | ||||
| -rw-r--r-- | board/esd/du405/flash.c | 107 | ||||
| -rw-r--r-- | board/esd/du405/fpgadata.c | 1405 | ||||
| -rw-r--r-- | configs/DU405_defconfig | 3 | ||||
| -rw-r--r-- | doc/README.scrapyard | 1 | ||||
| -rw-r--r-- | include/configs/DU405.h | 273 |
11 files changed, 1 insertions, 2033 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index e0eef94c9c..447a7733a0 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -125,9 +125,6 @@ config TARGET_CPCI405AB config TARGET_CPCI405DT bool "Support CPCI405DT" -config TARGET_DU405 - bool "Support DU405" - config TARGET_DU440 bool "Support DU440" @@ -241,7 +238,6 @@ source "board/csb472/Kconfig" source "board/dave/PPChameleonEVB/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" -source "board/esd/du405/Kconfig" source "board/esd/du440/Kconfig" source "board/esd/hh405/Kconfig" source "board/esd/hub405/Kconfig" diff --git a/board/esd/du405/Kconfig b/board/esd/du405/Kconfig deleted file mode 100644 index 2913fb9721..0000000000 --- a/board/esd/du405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DU405 - -config SYS_BOARD - default "du405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "DU405" - -endif diff --git a/board/esd/du405/MAINTAINERS b/board/esd/du405/MAINTAINERS deleted file mode 100644 index 5eff2a438d..0000000000 --- a/board/esd/du405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DU405 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/du405/ -F: include/configs/DU405.h -F: configs/DU405_defconfig diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile deleted file mode 100644 index 7914eab355..0000000000 --- a/board/esd/du405/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = du405.o flash.o ../common/misc.o diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c deleted file mode 100644 index 8f5f4d02a8..0000000000 --- a/board/esd/du405/du405.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "du405.h" -#include <asm/processor.h> -#include <asm/ppc4xx.h> -#include <asm/ppc4xx-i2c.h> -#include <command.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - - -#if 0 -#define FPGA_DEBUG -#endif - -#if 0 -#define FPGA_DEBUG2 -#endif - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - int index, len, i; - int status; - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive - * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive - * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive - * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive - * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 100 us - */ - mtebc (EBC0_CFG, 0xb8400000); - - return 0; -} - - -int misc_init_r (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * Setup UART1 handshaking: use CTS instead of DSR - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming DU405"); - } else { - puts (str); - } - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - /* - * Reset external DUART via FPGA - */ - out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */ - out_8((void *)FPGA_MODE_REG, 0x00); /* low again */ - - return 0; -} - -void reset_phy(void) -{ -#if defined(CONFIG_LXT971_NO_SLEEP) - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h deleted file mode 100644 index 292f196304..0000000000 --- a/board/esd/du405/du405.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c deleted file mode 100644 index 5650e5eaf2..0000000000 --- a/board/esd/du405/flash.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c deleted file mode 100644 index 262f2ca223..0000000000 --- a/board/esd/du405/fpgadata.c +++ /dev/null @@ -1,1405 +0,0 @@ -0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, -0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d, -0x64, 0x75, 0x72, 0x61, 0x67, 0x34, 0x30, 0x35, -0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, -0x73, 0x32, 0x30, 0x78, 0x6c, 0x74, 0x71, 0x31, -0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, -0x30, 0x32, 0x2f, 0x30, 0x32, 0x2f, 0x32, 0x31, -0x00, 0x64, 0x00, 0x09, 0x31, 0x32, 0x3a, 0x35, -0x31, 0x3a, 0x30, 0x38, 0x00, 0x65, 0xe2, 0x01, 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0x05, 0x03, 0x01, 0x0d, -0x03, 0x01, 0x03, 0x07, 0x09, 0x09, 0x09, 0x09, -0x03, 0x05, 0x09, 0x09, 0x11, 0x13, 0x01, 0xe5, -0x0a, 0x06, 0x09, 0x09, 0x04, 0x01, 0x02, 0x01, -0x03, 0x07, 0x05, 0x09, 0x01, 0x03, 0x07, 0x0e, -0xe5, 0x02, 0x06, 0xe5, 0x02, 0x04, 0x04, 0x01, -0x07, 0x04, 0x04, 0x05, 0x03, 0x01, 0x07, 0x01, -0x07, 0x01, 0x03, 0x03, 0x02, 0x04, 0x04, 0x06, -0x01, 0x03, 0xe5, 0xe5, 0xe6, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, diff --git a/configs/DU405_defconfig b/configs/DU405_defconfig deleted file mode 100644 index fdfe41bee9..0000000000 --- a/configs/DU405_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_DU405=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 6f7598f834..c650a1d46b 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu> DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu> CPCIISER4 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu> CMS700 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu> diff --git a/include/configs/DU405.h b/include/configs/DU405.h deleted file mode 100644 index 9be2310dbd..0000000000 --- a/include/configs/DU405.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_DU405 1 /* ...on a DU405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "bootm fff00000" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -#undef CONFIG_HAS_ETH1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_EDITENV -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_IDE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (CAT24WC08) for environment - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ - /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART_BA 0xF0300000 /* DUART Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define SRAM_BA 0xF0200000 /* SRAM Base Address */ -#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */ -#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */ - -#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (CAN0) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 3 (DUART) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 4 (CompactFlash IDE) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 5 (SRAM) initialization */ -#define CONFIG_SYS_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 6 (DURAG Bus IO Space) initialization */ -#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/ - -/* Memory Bank 7 (DURAG Bus Mem Space) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */ - - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#endif /* __CONFIG_H */ |