diff options
203 files changed, 9483 insertions, 3191 deletions
@@ -1,3 +1,393 @@ +commit 6923565db12af34fd5e02d354ee65a8c78ac460f +Author: Detlev Zundel <dzu@denx.de> +Date: Fri Apr 20 12:01:47 2007 +0200 + + Fix breakage of NC650 board with respect to nand support. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit 39f23cd90947639ac278a18ff277ec786b5ac167 +Author: Domen Puncer <domen.puncer@telargo.com> +Date: Fri Apr 20 11:13:16 2007 +0200 + + [RFC PATCH] icecube/lite5200b: fix OF_TBCLK (timebase-frequency) calculation + + G2 core reference manual says decrementer and time base + are decreasing/increasing once every 4 bus clock cycles. + Lets fix it, so time in Linux won't run twice as fast + + Signed-off-by: Domen Puncer <domen.puncer@telargo.com> + Acked-by: Grant Likely <grant.likely@secretlab.ca> + +commit 7651f8bdbba03bb0b4f241e2d2c4cb65b230bd56 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Thu Apr 19 23:14:39 2007 -0400 + + Fix serious pointer bug with bootm and reserve map. + + What was suppose to be a stack variable was declared as a pointer, + overwriting random memory. + Also moved the libfdt.a requirement into the main Makefile. That is + The U-Boot Way. + +commit 37837828d89084879bee2f2b8c7c68d4695940df +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 18 17:49:29 2007 +0200 + + Clenaup, update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit fd094c6379e2ef8a4d0ceb5640b24cb0c8d04449 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 18 17:20:58 2007 +0200 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 2a26ec4732efd7a308d0bbc97714c1d75ef1173b +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 18 17:07:26 2007 +0200 + + Cleanup, update CHANGELOG + + Sigend-off-by: Wolfgang Denk <wd@denx.de> + +commit 5f6c732affea9647762d27a4617a2ae64c52dceb +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 18 16:17:46 2007 +0200 + + Update CHANGELOG + +commit ad4eb555671d97f96dc56eab55103b1f86874b01 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Apr 18 14:30:39 2007 +0200 + + MCC200 board: remove warning which is obsolete after PSoC firmware changes + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 3747a3f010b2b1442dec3e871c69788b6017aaae +Author: Domen Puncer <domen.puncer@telargo.com> +Date: Wed Apr 18 12:11:05 2007 +0200 + + [PATCH] icecube/lite5200b: document wakeup from low-power support + + Signed-off-by: Domen Puncer <domen.puncer@telargo.com> + +commit e673226ff9d6aa91b47ceac74b8c13770b06bb37 +Author: Stefan Roese <sr@denx.de> +Date: Wed Apr 18 12:07:47 2007 +0200 + + ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 90e6f41cf09fc98f6ccb510e183d53ab8546cf2f +Author: Stefan Roese <sr@denx.de> +Date: Wed Apr 18 12:05:59 2007 +0200 + + ppc4xx: Add output for bootrom location to 405EZ ports + + Now 405EZ ports also show upon bootup from which boot device + they are configured to boot: + + U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) + + CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) + Bootstrap Option E - Boot ROM Location EBC (32 bits) + 16 kB I-Cache 16 kB D-Cache + Board: Acadia - AMCC PPC405EZ Evaluation Board + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 9c00dfb0bf89c8c23e8af5b5bdf49cf66d769f85 +Author: Peter Pearse <peter.pearse@arm.com> +Date: Tue Apr 17 13:30:33 2007 +0100 + + Move ppearse to ARM board list + Add Konstantin Kletschke for scb9328. + Signed-off-by: Peter Pearse <peter.pearse@arm.com> + +commit d3832e8fe1b214ec62424eac36cfda9fc56d21b3 +Author: Domen Puncer <domen.puncer@telargo.com> +Date: Mon Apr 16 14:00:13 2007 +0200 + + [PATCH] icecube/lite5200b: wakeup from low-power support + + U-Boot part of Lite5200b low power mode support. + Puts SDRAM out of self-refresh and transfers control to + address saved at physical 0x0. + + Signed-off-by: Domen Puncer <domen.puncer@telargo.com> + Acked-by: Grant Likely <grant.likely@secretlab.ca> + +commit f35a53fc7b0c79fcfe7bdc01163c4b34aaba1460 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Sun Apr 15 13:54:26 2007 -0400 + + Fix the ft_cpu_setup() property settings. + + Use "setter" functions instead of flags, cleaner and more flexible. + It also fixes the problem noted by Timur Tabi that the ethernet MAC + addresses were all being set incorrectly to the same MAC address. + +commit c28abb9c614f65ce2096cc4a66fc886c77d0e5a4 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Sat Apr 14 22:51:24 2007 -0400 + + Improve the bootm command for CONFIG_OF_LIBFDT + + In bootm, create the "/chosen" node only if it doesn't already exist + (better matches the previous behavior). + Update for proper reserved memory map handling for initrd. + +commit 3f9f08cf91c8a6949a5d78a18bd3d8df7b86d888 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Sat Apr 14 22:46:41 2007 -0400 + + Add some utilities to manipulate the reserved memory map. + +commit 8048cdd56f04a756eeea4951f402bf5cc33785db +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Apr 14 21:16:54 2007 +0200 + + Update CHANGELOG + +commit 8e6875183cdca91c134408d119d4abcd48ef6856 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 18:56:46 2006 +0100 + + AVR32: Enable MMC support + + Set up the portmux for the MMC interface and enable the MMC driver + along with support for DOS partitions, ext2 and FAT filesystems. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit fc26c97bb6df41b4a95662c34054fe912387bf38 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Jan 20 10:03:53 2006 +0100 + + Atmel MCI driver + + Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs. + + The AT91 ARM-based CPUs use basically the same hardware, so it should + be possible to share this driver, but no effort has been made so far. + + Hardware documentation can be found in the AT32AP7000 data sheet, + which can be downloaded from + + http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 05fdab1ef6a10d049a50021a86f1226f444d9b9f +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 18:55:37 2006 +0100 + + AVR32: Add clk and gpio infrastructure for mmci + + Implement functions for configuring the mmci pins, as well as + functions for getting the clock rate of the mmci controller. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 7fac3f69e9f05c5e5326681976c35d129324c4de +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 18:53:56 2006 +0100 + + Enable partition support with MMC + + Include implementations of init_part() and get_partition_info() when + CONFIG_MMC is set. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 9a24f477a1ed5bb0f74377c985d754ebbfa44872 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 17:14:30 2006 +0100 + + AVR32: Enable networking + + Implement MACB initialization for AVR32 and ATSTK1000, and turn + everything on, including the MACB driver. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 5c1fe1ffffd1750a7e47e5a2e2cd600c00e4f009 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Fri Jan 20 10:03:34 2006 +0100 + + Atmel MACB ethernet driver + + Driver for the Atmel MACB on-chip ethernet controller. + + This driver has been tested on the ATSTK1000 board with a AT32AP7000 + CPU. It should probably work on AT91SAM926x as well with some minor + modifications. + + Hardware documentation can be found in the AT32AP7000 data sheet, + which can be downloaded from + + http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit b4ec9c2d43d894729bb633bfdbdfa95a962c1556 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 16:56:14 2006 +0100 + + AVR32: Add clk and gpio infrastructure for macb0 and macb1 + + Implement functions for configuring the macb0 and macb1 pins, as + well as functions for getting the clock rate of the various + busses the macb ethernet controllers are connected to. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit d5acb95b16a0a74c643524342c3437e765426d05 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 15:39:15 2006 +0100 + + AVR32: Implement simple DMA memory allocator + + Implement dma_alloc_coherent() which returns cache-aligned + uncacheable memory. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 91975b0fea773c9e681fea8cf3349669f27685ee +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 15:46:02 2006 +0100 + + Import <linux/mii.h> from the Linux kernel + + Instead of creating yet another set of MII register definitions + in the macb driver, here's a complete set of definitions for everyone + to use. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 1b804b229556a4d862da93c0ec94e79419364b2c +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Wed Mar 21 19:47:36 2007 +0100 + + AVR32: Include more commands for ATSTK1000 + + Include the imi, imls and jffs commands sets by default on ATSTK1000. + Also define CONFIG_BOOTARGS to something more useful, define + CONFIG_BOOTCOMMAND and enable autoboot by default. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 9c0deb5ae3ea0189f2e08ac29ef1316f1fb8548d +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Wed Mar 21 19:44:48 2007 +0100 + + AVR32: Provide a definition of struct stat + + Copy the definition of struct stat from the Linux kernel. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 12f099c08167a7a51aeee623bc16dafd0841271c +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Dec 17 14:46:06 2006 +0100 + + AVR32: Use initdram() instead of board_init_memories() + + Conform to the "standard" interface and use initdram() instead of + board_init_memories() on AVR32. This enables us to get rid of the + sdram_size member of the global_data struct as well. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 1f4f2121c2685182eb87fa9a9b799d1917387a1c +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Mon Nov 20 15:53:10 2006 +0100 + + AVR32: Relocate u-boot to SDRAM + + Relocate the u-boot image into SDRAM like everyone else does. This + means that we can handle much larger .data and .bss than we used to. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit df548d3c3e2bbc40258713167859ffc2ce99a900 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sun Nov 19 18:06:53 2006 +0100 + + AVR32: Resource management rewrite + + Rewrite the resource management code (i.e. I/O memory, clock gating, + gpio) so it doesn't depend on any global state. This is necessary + because this code is heavily used before relocation to RAM, so we + can't write to any global variables. + + As an added bonus, this makes u-boot's memory footprint a bit smaller, + although some functionality has been left out; all clocks are enabled + all the time, and there's no checking for gpio line conflicts. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 03d1e1365796cd15d1726e8a51fd8b5be50b2fe9 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sat Nov 18 18:01:13 2006 +0100 + + AVR32: Clean up memory-map.h for at32ap7000 + + Convert spaces to tabs (must have missed this one last time around), + sort the entries by address and group them together by bus + connectivity. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 28c699ef69f4b6cdf252e4747b7b590028a88981 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sat Nov 18 17:32:31 2006 +0100 + + AVR32: Build position-independent u-boot + + Add -fPIC -mno-init-got to the avr32-specific CFLAGS to make u-boot + position independent. This will make relocation a lot easier. + + -mno-init-got means that gcc shouldn't emit code to load the GOT + address into r6 in every function prologue. We do it once and for + all in the early startup assembly code, so enabling this option + makes u-boot a bit faster and smaller. + + The assembly parts have always been position-independent, so no code + changes should be necessary. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit 5374b36de91d006d1df9536259fa9f66b01aa3aa +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sat Nov 18 17:24:31 2006 +0100 + + AVR32: Use avr32-linux- cross-compilation prefix by default + + It doesn't really matter which toolchain you use to compile u-boot, + but the avr32-linux one is probably what most people have installed. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + +commit c841beeddebece0039e724fb27f4d1a39ee1c6b6 +Author: Haavard Skinnemoen <hskinnemoen@atmel.com> +Date: Sat Nov 18 17:15:30 2006 +0100 + + AVR32: Split start_u_boot into board_init_f and board_init_r + + Split the avr32 initialization code into a function to run before + relocation, board_init_f and a function to run after relocation, + board_init_r. For now, board_init_f simply calls board_init_r + at the end. + + Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> + commit 37403005cfe6bb13964d450f6a48a0b0f2f7017e Author: Heiko Schocher <hs@pollux.denx.de> Date: Sat Apr 14 05:26:48 2007 +0200 @@ -7,6 +397,42 @@ Date: Sat Apr 14 05:26:48 2007 +0200 Signed-off-by: Heiko Schocher <hs@denx.de> +commit 7882751c78b7ecabfd49b0eff8de27661c71f16c +Author: Denis Peter <d.peter@mpl.ch> +Date: Fri Apr 13 09:13:33 2007 +0200 + + [PATCH] Fix bugs in cmd_ide.c and cmd_scsi.c + + Fix bug introduced by "Fix get_partition_info() parameter error in all + other calls" from 2005-03-04 in cmd_ide.c and cmd_scsi.c, which prevented + to use diskboot or scsiboot form another device than 0. + + Signed-off-by: Denis Peter <d.peter@mpl.ch> + +commit 0b94504d22e70f537c17a0d38c87edb6e370977d +Author: Greg Lopp <lopp@pobox.com> +Date: Fri Apr 13 08:02:24 2007 +0200 + + [PATCH] Fix use of "void *" for block dev read/write buffer pointers + + Signed-of-by: Greg Lopp <lopp@pobox.com> + Acked-by: Grant Likely <grant.likely@secretlab.ca> + +commit 2ad3aba01d37b72e7c957b07e102fccd64fe6d13 +Author: Jeffrey Mann <mannj@embeddedplanet.com> +Date: Thu Apr 12 14:15:59 2007 +0200 + + ppc4xx: Fix i2c divisor calcularion for PPC4xx + + This patch fixes changes the i2c_init(...) function to use the function + get_OPB_freq() rather than calculating the OPB speed by + sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is + specific per processor. The prior method was not and so was calculating + the wrong speed for some PPC4xx processors. + + Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> + Signed-off-by: Stefan Roese <sr@denx.de> + commit 6c9ba919375db977aaad9146bf320c7afd07ae7a Author: Wolfgang Denk <wd@denx.de> Date: Wed Apr 11 17:25:01 2007 +0200 @@ -25,6 +451,106 @@ Date: Wed Apr 11 17:22:55 2007 +0200 * Use Newline as "password" string * Use just a single partition in NAND flash +commit 3d98b85800c80dc68227c8f10bf5c93456d6d054 +Author: Haiying Wang <haiying.wang@freescale.com> +Date: Mon Jan 22 12:37:30 2007 -0600 + + Add PIXIS FPGA support for MPC8641HPCN board. + + Move the 8641HPCN's PIXIS code to the new directory + board/freescale/common/ as it will be shared by + future boards not in the same processor family. + + Write a "pixis_reset" command that utilizes the FPGA + reset sequencer to support alternate soft-reset options + such as using the "alternate" flash bank, enabling + the watch dog, or choosing different CPU frequencies. + + Add documentation for the pixis_reset to README.mpc8641hpcn. + + Signed-off-by: Haiying Wang <haiying.wang@freescale.com> + Signed-off-by: Jon Loeliger <jdl@freescale.com> + +commit 64dbbd40c58349b64f43fd33dbb5ca0adb67d642 +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Fri Apr 6 14:19:43 2007 -0400 + + Moved fdt command support code to fdt_support.c + + ...in preparation for improving the bootm command's handling of fdt blobs. + Also cleaned up some coding sloppiness. + +commit 6679f9299534e488a171a9bb8f9bb891de247aab +Author: Gerald Van Baren <vanbaren@cideas.com> +Date: Fri Apr 6 14:17:14 2007 -0400 + + libfdt: Make fdt_check_header() public + + Changed _fdt_check_header() to fdt_check_header() and made it part of + the interface - it is a useful routine. + + Also did some asthetics cleanup to the include files (headers). + +commit c0707ce65677650b5ceab0500ee50ae5168afef2 +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:34:06 2007 +0800 + + [Blackfin][PATCH] Kill off a bunch of common local prototypes + +commit 7b7e30aa64bb6657a1bfd32fdbdbfeb561e6a48d +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:33:04 2007 +0800 + + [Blackfin][PATCH] Fix dynamic CPLB generation issue + +commit 0445e3a264251d75b1be45ef713c70726a2952f0 +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:31:47 2007 +0800 + + [Blackfin][PATCH] minior cleanup + +commit 155fd766573981090e638b493d5857562151862e +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:31:18 2007 +0800 + + [Blackfin][PATCH] Fix copyright and update license + +commit 9fd437bbd75d282f899e1da50be20a2bf38450bc +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:30:25 2007 +0800 + + [Blackfin][PATCH] Add BF537 EMAC driver initialization + +commit 889256e8604e0c68db1d866d720894dffede9df6 +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:29:55 2007 +0800 + + [Blackfin][PATCH] call real the system synchronize instruction + +commit e0df1c921b788289564e4c1ee7120a6a9cd3ab05 +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:29:17 2007 +0800 + + [Blackfin][PATCH] remove asm/page.h as we do not actually use/want any of these definitions nor does any other arch include it + +commit dfeeab2cd680df047e68e723b246adf6f33bb556 +Author: Aubrey Li <aubrey.adi@gmail.com> +Date: Thu Apr 5 18:28:34 2007 +0800 + + [Blackfin][PATCH]: fix flash unaligned copy issue + +commit 443feb740584e406efa203af909fe2926608e8d5 +Author: Igor Marnat <marny@rambler.ru> +Date: Wed Mar 21 09:55:01 2007 +0300 + + Update usage of 'nc' in README.NetConsole + + Added information about usage of NetConsole on systems where the -l and -p + switches are mutually exclusive. + + Signed-off-by: Igor Marnat <marny@rambler.ru> + Signed-off-by: Ben Warren <bwarren@qstreams.com> + commit 31c98a88228021b314c89ebb8104fb6473da4471 Author: Wolfgang Denk <wd@denx.de> Date: Wed Apr 4 02:09:30 2007 +0200 @@ -37,6 +563,18 @@ Date: Wed Apr 4 01:49:15 2007 +0200 Minor cleanup. +commit a65c5768e5537530bd1780af3d3fddc3113a163c +Author: Stefan Roese <sr@denx.de> +Date: Mon Apr 2 10:09:30 2007 +0200 + + ppc4xx: Change SysACE address on Katmai + + With this new base address of the Xilinx SystemACE controller + the Linux driver will be easier to adapt, since it can now be + mapped via the "normal" ioremap() call. + + Signed-off-by: Stefan Roese <sr@denx.de> + commit aea03c4e8c3a21ce43d3faf48a6e6d474c8bdf73 Author: Gerald Van Baren <vanbaren@cideas.com> Date: Sat Mar 31 14:30:53 2007 -0400 @@ -604,6 +1142,24 @@ Date: Thu Mar 8 10:06:09 2007 +0100 Signed-off-by: Stefan Roese <sr@denx.de> +commit 83853178bd36bca6f0f8f1331476620c84a587fc +Author: Ed Swarthout <Ed.Swarthout@freescale.com> +Date: Wed Mar 7 12:14:50 2007 -0600 + + net - Support ping reply when processing net-loop + + Add ICMP_ECHO_REQUEST packet support by responding with a ICMP_ECHO_REPLY. + + This permits the ping command to test the phy interface when the phy + is put in loopback mode (typically by setting register 0 bit 14). + + It also allows the port to respond to an external ping when u-boot is + processing some other net command (such as tftp). This is useful when + tftp appears to hang. + + Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> + Signed-off-by: Ben Warren <bwarren@qstreams.com> + commit fa1aef15bcd47736687be1af544506e90fba545d Author: Stefan Roese <sr@denx.de> Date: Wed Mar 7 16:43:00 2007 +0100 @@ -680,6 +1236,12 @@ Date: Tue Mar 6 07:47:04 2007 +0100 Signed-off-by: Stefan Roese <sr@denx.de> +commit 647d3c3eed0da1d1505eecabe0b0fab96f956e68 +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Sun Mar 4 01:36:05 2007 +0100 + + Some code cleanup. + commit 781e026c8aa6f7e9eb5f0e72cc4d20971219b148 Author: Kim Phillips <kim.phillips@freescale.com> Date: Wed Feb 28 00:02:04 2007 -0600 @@ -1551,6 +2113,15 @@ Date: Tue Jan 23 13:25:22 2007 +0100 [ColdFire MCF5271 family] Add CPU detection based on the value of Chip Identification Register (CIR). +commit fdef388758506765d4d6a7155c8f1584c63ff581 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Mon Jan 22 13:19:21 2007 +0800 + + use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP + The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007 + fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support + mpc7448hpc2 board. + commit a4012396645533aef218354eeba754dff0deace8 Author: Wolfgang Denk <wd@pollux.denx.de> Date: Fri Jan 19 23:08:39 2007 +0100 @@ -1966,6 +2537,72 @@ Date: Fri Dec 8 16:23:08 2006 +0100 automatic update mechanism +commit 9d27b3a0685ff99fc477983f315c04d49f657a8a +Author: roy zang <tie-fei.zang@freescale.com> +Date: Mon Dec 4 17:56:59 2006 +0800 + + Slight code clean up. + Add comments, delete duplicate define and remove spaces. + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 4dbcd69e3e2776ea334590d5768e3692c5fae5c1 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Mon Dec 4 17:54:21 2006 +0800 + + Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original + multiplier table can not refect the real PLL clock behavior of these + processors. Please refer to the hardware specification for detailed + information of the corresponding processors. + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 4efe20c9579011d9987f62ed7d35ee8cdc1cf0e0 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Mon Dec 4 14:46:23 2006 +0800 + + Remove the static MAC address, ip address, server ip, netmask and + gateway ip for network setting. + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 6f12c61cf31ed73d72ddfcfc712a854a3a177aaf +Author: roy zang <tie-fei.zang@freescale.com> +Date: Mon Dec 4 14:33:08 2006 +0800 + + Remove the duplicate memory test code for mpc744ihpc2 board. + If a memory test is needed, please use the functions in + post/memory.c or memtest command. + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit c9c1eeed7dd193fa65fb194654132040d49d4d3a +Author: roy zang <tie-fei.zang@freescale.com> +Date: Fri Dec 1 19:01:25 2006 +0800 + + Fix the exception occuring in RAM table search issue. + The original search_one_table() function code can only processes the search + for the exception occurring in FLASH/ROM, because the exception and fixup + table usually locate in FLASH. If the exception address is also in + FLASH, it will be OK. + If the exception occurs in RAM, after the u-boot relocation, a + relocation offset should be added. + + clean up the code in cpu/74xx_7xx/cpu.c + + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit ee311214e0d216f904feea269599d0934bf71f23 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Fri Dec 1 11:47:36 2006 +0800 + + Clean up the code according to codestyle: + (1) remove some C++ comments. + (2) remove trailing white space. + (3) remove trailing empty line. + (4) Indentation by table. + (5) remove {} in one line condition. + (6) add space before '(' in function call. + Remove some weird printf () output. + Add necessary comments. + Modified Makefile to support building in a separate directory. + commit dd520bf314c7add4183c5191692180f576f96b60 Author: Wolfgang Denk <wd@pollux.denx.de> Date: Thu Nov 30 18:02:20 2006 +0100 @@ -2672,12 +3309,191 @@ Date: Thu Sep 7 07:39:46 2006 -0700 Signed-off-by: Nick Spence <nick.spence@freescale.com> +commit 4831c8b8a97799da77923d6bbb4c260c0d45521c +Author: roy zang <tie-fei.zang@freescale.com> +Date: Fri Nov 3 13:10:00 2006 +0800 + + Remove some unused CFG define. + undef CFG_DRAM_TEST + +commit 99c09c4dec34f77c243bf51bea532e3f339410ad +Author: roy zang <tie-fei.zang@freescale.com> +Date: Fri Nov 3 13:07:36 2006 +0800 + + Change the TEXT_BASE from 0xFFF00000 to 0xFF000000. + Both work. 0xFF000000 seems more reasonable. + commit c59200443072353044aa4bf737a5a60f9a9af231 Author: Wolfgang Denk <wd@pollux.denx.de> Date: Thu Nov 2 15:15:01 2006 +0100 Release U-Boot 1.1.6 +commit c1fbe4103a0d6c8957f912af902d705ba67836f2 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 19:14:48 2006 +0800 + + This patch comes from Yuli's posted patch on 8/8/2006 + titled "CFI Driver Little-Endian write Issue". + + http://sourceforge.net/mailarchive/message.php?msg_id=36311999 + + If that patch applied, please discard this one. + Until now , I do not see his patch is applied. So please apply this one. + + Signed-off-by: Yuli Barcohen <yuli@arabellasw.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit b825f158e449e1e9cf74c08e572955e122394c96 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 19:12:31 2006 +0800 + + Tsi108 on chip i2c support. + + The i2c Interface provides a master-only, serial interface that can be + used for initializing Tsi108/Tsi109 registers from an EEPROM after a + device reset. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 9226e7d6f09b9a1ac074cd918c81225a4689bba8 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 19:11:06 2006 +0800 + + Tsi108 on chip pci controller support. + + If there is no pci card, the tsi108/109 pci configure read will + cause a machine check exception to the processor. PCI error should + also be cleared after the read. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit d1927cee977126e547ceeba23e4f978f377cfb8f +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 19:08:55 2006 +0800 + + Tundra tsi108 on chip Ethernet controller support. + + The following is a brief description of the Ethernet controller: + The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent + Gigabit Ethernet ports,E0 and E1. It uses a single Management interface + to manage the two physical connection devices (PHYs). Each Ethernet port + has its own statistics monitor that tracks and reports key interface + statistics. Each port supports a 256-entry hash table for address + filtering. In addition, each port is bridged to the Switch Fabric + through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. + + Each Ethernet port also has a pair of internal Ethernet DMA channels to + support the transmit and receive data flows. The Ethernet DMA channels + use descriptors set up in memory, the memory map of the device, and + access via the Switch Fabric. The Ethernet Controller?s DMA arbiter + handles arbitration for the Switch Fabric. The Controller also + has a register businterface for register accesses and status monitor + control. + + The PMD (Physical Media Device) interface operates in MII, GMII, or TBI + modes. The MII mode is used for connecting with 10 or 100 Mbit/s PMDs. + The GMII and TBI modes are used to connect with Gigabit PMDs. Internal + data flows to and from the Ethernet Controller through the Switch Fabric. + + Each Ethernet port uses its transmit and receive DMA channels to manage + data flows through buffer descriptors that are predefined by the + system (the descriptors can exist anywhere in the system memory map). + These descriptors are data structures that point to buffers filled + with data ready to transmit over Ethernet, or they point to empty + buffers ready to receive data from Ethernet. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 78aa0c3427f3ecdeb34aabfbbe2dd23b6ad8f40e +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 19:01:33 2006 +0800 + + Tundra tsi108 header file. + + The Tundra Semiconductor Corporation (Tundra) Tsi108 is a host bridge for + PowerPC processors that offers numerous system interconnect options for + embedded application designers. The Tsi108 can interconnect 60x or + MPX processors to PCI/X peripherals, DDR2-400 memory, Gigabit Ethernet, + and Flash. Provided the macro define for tsi108 chip. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 87c4db09699c6b89176b31004afcb83eb1585d47 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 18:59:15 2006 +0800 + + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 27801b8ab11c61b577e45742a515bb3b23b80241 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 18:57:21 2006 +0800 + + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Make ,config.mk and link file for the mpc7448hpc2 board. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 18:55:04 2006 +0800 + + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + The mpc7448hpc2 board support header file. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 625bb5ddb50b243f931262ca8c46956409471917 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 18:52:21 2006 +0800 + + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + The mpc7448hpc2 board support low level assemble language init code. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 4c52783b3d024e153c4972b97332e314bc3bdc46 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 18:49:51 2006 +0800 + + General code modification for mpc7448hpc2 board support. + 1. Add 7447A and 7448 processor support. + 2. Add the following flags. + + CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically + (such as by switch on board), this flag should be set. + + CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot + relocates to RAM, this flag should be set. + + CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the + system hang in exception, this flag should be set. + + There is a design issue for tsi108/109 pci configure read. When pci scan + the slots, if there is no pci card, the tsi108/9 will cause a machine + check exception for mpc7448 processor. + + Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + +commit 69366bf42f22d67efce8da3f8c40a43d4a3c2695 +Author: roy zang <tie-fei.zang@freescale.com> +Date: Thu Nov 2 18:34:47 2006 +0800 + + Add README file for mpc7448hpc2 board. + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> + commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526 Author: Bartlomiej Sieka <tur@semihalf.com> Date: Wed Nov 1 02:04:38 2006 +0100 diff --git a/MAINTAINERS b/MAINTAINERS index 2a43848fc9..c3c73da4f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -257,15 +257,6 @@ Frank Panno <fpanno@delphintech.com> ep8260 MPC8260 -Peter Pearse <peter.pearse@arm.com> - integratorcp All current ARM supplied & - supported core modules - - see http://www.arm.com - /products/DevTools - /Hardware_Platforms.html - versatile ARM926EJ-S - versatile ARM926EJ-S - Denis Peter <d.peter@mpl.ch> MIP405 PPC4xx @@ -444,6 +435,9 @@ Gary Jennejohn <gj@denx.de> smdk2400 ARM920T trab ARM920T +Konstantin Kletschke <kletschke@synertronixx.de> + scb9328 ARM920T + Nishant Kamat <nskamat@ti.com> omap1610h2 ARM926EJS @@ -461,6 +455,15 @@ Rolf Offermanns <rof@sysgo.de> shannon SA1100 +Peter Pearse <peter.pearse@arm.com> + integratorcp All current ARM supplied & + supported core modules + -see http://www.arm.com + /products/DevTools + /Hardware_Platforms.html + versatile ARM926EJ-S + versatile ARM926EJ-S + Dave Peverley <dpeverley@mpc-data.co.uk> omap730p2 ARM926EJS @@ -155,6 +155,7 @@ LIST_85xx=" \ LIST_74xx=" \ DB64360 DB64460 EVB64260 P3G4 \ p3m7448 PCIPPC2 PCIPPC6 ZUMA \ + mpc7448hpc2 " LIST_7xx=" \ @@ -149,7 +149,7 @@ ifeq ($(ARCH),blackfin) CROSS_COMPILE = bfin-uclinux- endif ifeq ($(ARCH),avr32) -CROSS_COMPILE = avr32- +CROSS_COMPILE = avr32-linux- endif endif endif @@ -219,6 +219,7 @@ LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \ LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \ "post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi) LIBS += common/libcommon.a +LIBS += libfdt/libfdt.a LIBS += $(BOARDLIBS) LIBS := $(addprefix $(obj),$(LIBS)) @@ -1819,6 +1820,9 @@ EVB64260_config \ EVB64260_750CX_config: unconfig @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260 +mpc7448hpc2_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 + P3G4_config: unconfig @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 @@ -2398,17 +2398,17 @@ configurations; the following names are supported: csb272_config lwmon_config sbc8260_config CU824_config MBX860T_config sbc8560_33_config DUET_ADS_config MBX_config sbc8560_66_config - EBONY_config MPC8260ADS_config SM850_config - ELPT860_config MPC8540ADS_config SPD823TS_config - ESTEEM192E_config MPC8540EVAL_config stxgp3_config - ETX094_config MPC8560ADS_config SXNI855T_config - FADS823_config NETVIA_config TQM823L_config - FADS850SAR_config omap1510inn_config TQM850L_config - FADS860T_config omap1610h2_config TQM855L_config - FPS850L_config omap1610inn_config TQM860L_config - omap5912osk_config walnut_config - omap2420h4_config Yukon8220_config - ZPC1900_config + EBONY_config mpc7448hpc2_config SM850_config + ELPT860_config MPC8260ADS_config SPD823TS_config + ESTEEM192E_config MPC8540ADS_config stxgp3_config + ETX094_config MPC8540EVAL_config SXNI855T_config + FADS823_config NMPC8560ADS_config TQM823L_config + FADS850SAR_config NETVIA_config TQM850L_config + FADS860T_config omap1510inn_config TQM855L_config + FPS850L_config omap1610h2_config TQM860L_config + omap1610inn_config walnut_config + omap5912osk_config Yukon8220_config + omap2420h4_config ZPC1900_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for diff --git a/avr32_config.mk b/avr32_config.mk index 0b92053e1a..441caa405a 100644 --- a/avr32_config.mk +++ b/avr32_config.mk @@ -21,5 +21,5 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax +PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile index 155d46ac97..8a15713cc4 100644 --- a/board/atmel/atstk1000/Makefile +++ b/board/atmel/atstk1000/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o +COBJS := $(BOARD).o flash.o eth.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 4d737d293a..6618963cc0 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -23,6 +23,8 @@ #include <asm/io.h> #include <asm/sdram.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix2.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,9 +42,27 @@ static const struct sdram_info sdram = { .txsr = 5, }; -void board_init_memories(void) +int board_early_init_f(void) { - gd->sdram_size = sdram_init(&sdram); + /* Set the SDRAM_ENABLE bit in the HEBI SFR */ + hmatrix2_writel(SFR4, 1 << 1); + + gpio_enable_ebi(); + gpio_enable_usart1(); +#if defined(CONFIG_MACB) + gpio_enable_macb0(); + gpio_enable_macb1(); +#endif +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + + return 0; +} + +long int initdram(int board_type) +{ + return sdram_init(&sdram); } void board_init_info(void) diff --git a/cpu/at32ap/at32ap7000/hebi.c b/board/atmel/atstk1000/eth.c index 3b32adf1ea..3a7916efed 100644 --- a/cpu/at32ap/at32ap7000/hebi.c +++ b/board/atmel/atstk1000/eth.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2006 Atmel Corporation + * Copyright (C) 2005-2006 Atmel Corporation + * + * Ethernet initialization for the ATSTK1000 starterkit * * See file CREDITS for list of people who contributed to this * project. @@ -21,18 +23,16 @@ */ #include <common.h> -#include <asm/io.h> - -#include <asm/arch/hmatrix2.h> #include <asm/arch/memory-map.h> -#include <asm/arch/platform.h> -void cpu_enable_sdram(void) -{ - const struct device *hmatrix; +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - hmatrix = get_device(DEVICE_HMATRIX); +#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET) +void atstk1000_eth_initialize(bd_t *bi) +{ + int id = 0; - /* Set the SDRAM_ENABLE bit in the HEBI SFR */ - hmatrix2_writel(hmatrix, SFR4, 1 << 1); + macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]); + macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]); } +#endif diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 3aebf66ee2..958f4dc330 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -57,7 +57,7 @@ unsigned long flash_init(void) gd->bd->bi_flashstart = CFG_FLASH_BASE; gd->bd->bi_flashsize = CFG_FLASH_SIZE; - gd->bd->bi_flashoffset = __edata_lma - _text; + gd->bd->bi_flashoffset = _edata - _text; flash_info[0].size = CFG_FLASH_SIZE; flash_info[0].sector_count = 135; diff --git a/board/atmel/atstk1000/u-boot.lds b/board/atmel/atstk1000/u-boot.lds index ef89ea4dfa..34e347aecd 100644 --- a/board/atmel/atstk1000/u-boot.lds +++ b/board/atmel/atstk1000/u-boot.lds @@ -40,35 +40,38 @@ SECTIONS } . = ALIGN(32); __flashprog_end = .; + _etext = .; - . = ALIGN(8); .rodata : { *(.rodata) *(.rodata.*) } - _etext = .; - __data_lma = ALIGN(8); - . = 0x24000000; + . = ALIGN(8); _data = .; - .data : AT(__data_lma) { + .data : { *(.data) *(.data.*) } . = ALIGN(4); __u_boot_cmd_start = .; - __u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data); - .u_boot_cmd : AT(__u_boot_cmd_lma) { + .u_boot_cmd : { KEEP(*(.u_boot_cmd)) } __u_boot_cmd_end = .; + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + . = ALIGN(8); _edata = .; - __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start); - .bss : AT(__edata_lma) { + .bss : { *(.bss) *(.bss.*) } diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 4fe7d785f3..e55c1a78a8 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -1,7 +1,7 @@ # # U-boot - Makefile # -# Copyright (c) 2007 Analog Device Inc. +# Copyright (c) 2005-2007 Analog Device Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index feaeb00697..1dd4a3fe2e 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -1,7 +1,7 @@ /* * U-boot - ezkit533.c * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index e211918bc2..bd9e859e70 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -1,7 +1,7 @@ /* * U-boot - flash-defines.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __FLASHDEFINES_H__ @@ -60,7 +60,7 @@ void reset_flash(void); int erase_flash(void); int erase_block_flash(int, unsigned long); void unlock_flash(long lOffset); -int write_data(long lStart, long lCount, long lStride, int *pnData); +int write_data(long lStart, long lCount, uchar *pnData); int FillData(long lStart, long lCount, long lStride, int *pnData); int read_data(long lStart, long lCount, long lStride, int *pnData); int read_flash(long nOffset, int *pnValue); diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index 067a260906..299cdbae73 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -1,7 +1,7 @@ /* * U-boot - flash.c Flash driver for PSD4256GV * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. * * (C) Copyright 2000-2004 @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <asm/io.h> @@ -178,63 +178,66 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { int ret; - - ret = write_data(addr, cnt, 1, (int *)src); + int d; + if (addr % 2) { + read_flash(addr - 1 - CFG_FLASH_BASE, &d); + d = (int)((d & 0x00FF) | (*src++ << 8)); + ret = write_data(addr - 1, 2, (uchar *) & d); + if (ret == FLASH_FAIL) + return ERR_NOT_ERASED; + ret = write_data(addr + 1, cnt - 1, src); + } else + ret = write_data(addr, cnt, src); if (ret == FLASH_FAIL) return ERR_NOT_ERASED; return FLASH_SUCCESS; } -int write_data(long lStart, long lCount, long lStride, int *pnData) +int write_data(long lStart, long lCount, uchar * pnData) { long i = 0; - int j = 0; unsigned long ulOffset = lStart - CFG_FLASH_BASE; int d; - int iShift = 0; - int iNumWords = 2; - int nLeftover = lCount % 4; int nSector = 0; + int flag = 0; - for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { - for (iShift = 0, j = 0; (j < iNumWords); - j++, ulOffset += (lStride * 2)) { - if ((ulOffset >= INVALIDLOCNSTART) - && (ulOffset < INVALIDLOCNEND)) { - printf - ("Invalid locations, Try writing to another location \n"); - return FLASH_FAIL; - } - get_sector_number(ulOffset, &nSector); - read_flash(ulOffset, &d); - if (d != 0xffff) { - printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", - ulOffset); - return FLASH_FAIL; - } - unlock_flash(ulOffset); - if (write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { - printf("Error programming the flash \n"); - return FLASH_FAIL; - } - iShift += 16; - } + if (lCount % 2) { + flag = 1; + lCount = lCount - 1; } - if (nLeftover > 0) { - if ((ulOffset >= INVALIDLOCNSTART) - && (ulOffset < INVALIDLOCNEND)) + + for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) { + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &d); + if (d != 0xffff) { + printf + ("Flash not erased at offset 0x%x Please erase to reprogram \n", + ulOffset); return FLASH_FAIL; + } + unlock_flash(ulOffset); + d = (int)(pnData[i] | pnData[i + 1] << 8); + write_flash(ulOffset, d); + if (poll_toggle_bit(ulOffset) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + if ((i > 0) && (!(i % AFP_SectorSize2))) + printf("."); + } + if (flag) { get_sector_number(ulOffset, &nSector); read_flash(ulOffset, &d); if (d != 0xffff) { printf - ("Flash already programmed. Please erase to reprogram \n"); - printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d); + ("Flash not erased at offset 0x%x Please erase to reprogram \n", + ulOffset); return FLASH_FAIL; } unlock_flash(ulOffset); - if (write_flash(ulOffset, pnData[i]) < 0) { + d = (int)(pnData[i] | (d & 0xFF00)); + write_flash(ulOffset, d); + if (poll_toggle_bit(ulOffset) < 0) { printf("Error programming the flash \n"); return FLASH_FAIL; } diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h index 97765165f8..cc654b8956 100644 --- a/board/bf533-ezkit/psd4256.h +++ b/board/bf533-ezkit/psd4256.h @@ -1,7 +1,7 @@ /* * U-boot - psd4256.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 8223d591ce..02c941b5a5 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -1,7 +1,7 @@ # # U-boot - Makefile # -# Copyright (c) 2007 Analog Device Inc. +# Copyright (c) 2005-2007 Analog Device Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 2f6e75187b..b9dff99171 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -1,7 +1,7 @@ /* * U-boot - stamp.c STAMP board specific routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h index b2b51aa2ba..1e58e47546 100644 --- a/board/bf533-stamp/bf533-stamp.h +++ b/board/bf533-stamp/bf533-stamp.h @@ -1,7 +1,7 @@ /* * U-boot - stamp.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __STAMP_H__ diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index cc4e9985fe..47f7c9edf6 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -1,7 +1,7 @@ /* * U-boot - BF537.c * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h index f19e171d04..acc1e8638b 100644 --- a/board/bf537-stamp/flash-defines.h +++ b/board/bf537-stamp/flash-defines.h @@ -1,7 +1,7 @@ /* * U-boot - flash-defines.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __FLASHDEFINES_H__ diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c index 42dcf062b1..ed85841479 100644 --- a/board/bf537-stamp/flash.c +++ b/board/bf537-stamp/flash.c @@ -1,7 +1,7 @@ /* * U-boot - flash.c Flash driver for PSD4256GV * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. * * (C) Copyright 2000-2004 @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <malloc.h> diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 71281c0139..989b0194c1 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -2,7 +2,7 @@ * U-boot - ezkit561.c * * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl> - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/board/mpc8641hpcn/pixis.c b/board/freescale/common/pixis.c index 964a17ca08..af98157dfd 100644 --- a/board/mpc8641hpcn/pixis.c +++ b/board/freescale/common/pixis.c @@ -23,14 +23,25 @@ */ #include <common.h> -#include <watchdog.h> #include <command.h> +#include <watchdog.h> #include <asm/cache.h> -#include <mpc86xx.h> #include "pixis.h" +static ulong strfractoint(uchar *strptr); + + +/* + * Simple board reset. + */ +void pixis_reset(void) +{ + out8(PIXIS_BASE + PIXIS_RST, 0); +} + + /* * Per table 27, page 58 of MPC8641HPCN spec. */ @@ -235,7 +246,8 @@ void set_px_go_with_watchdog(void) } -int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) { u8 tmp; @@ -252,7 +264,7 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - diswd, 1, 0, disable_watchdog, + diswd, 1, 0, pixis_disable_watchdog_cmd, "diswd - Disable watchdog timer \n", NULL); @@ -263,7 +275,7 @@ U_BOOT_CMD( * input: strptr i.e. argv[2] */ -ulong strfractoint(uchar *strptr) +static ulong strfractoint(uchar *strptr) { int i, j, retval; int mulconst; @@ -319,3 +331,142 @@ ulong strfractoint(uchar *strptr) return retval; } + + +int +pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong val; + ulong corepll; + + /* + * No args is a simple reset request. + */ + if (argc <= 1) { + pixis_reset(); + /* not reached */ + } + + if (strcmp(argv[1], "cf") == 0) { + + /* + * Reset with frequency changed: + * cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + */ + if (argc < 5) { + puts(cmdtp->usage); + return 1; + } + + read_from_px_regs(0); + + val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); + + corepll = strfractoint(argv[3]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0 and VCTL\n"); + read_from_px_regs(1); + puts("Resetting board with values from "); + puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n"); + set_px_go(); + } else { + puts(cmdtp->usage); + return 1; + } + + while (1) ; /* Not reached */ + + } else if (strcmp(argv[1], "altbank") == 0) { + + /* + * Reset using alternate flash bank: + */ + if (argv[2] == 0) { + /* + * Reset from alternate bank without changing + * frequency and without watchdog timer enabled. + * altbank + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if (argc > 2) { + puts(cmdtp->usage); + return 1; + } + puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Resetting board to boot from the other bank.\n"); + set_px_go(); + + } else if (strcmp(argv[2], "cf") == 0) { + /* + * Reset with frequency changed + * altbank cf <SYSCLK freq> <COREPLL ratio> + * <MPXPLL ratio> + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); + corepll = strfractoint(argv[4]); + val = val + set_px_corepll(corepll); + val = val + set_px_mpxpll(simple_strtoul(argv[5], + NULL, 10)); + if (val == 3) { + puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs(1); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA\n"); + puts("Resetting board with values from "); + puts("VSPEED0, VSPEED1, VCLKH and VCLKL "); + puts("to boot from the other bank.\n"); + set_px_go_with_watchdog(); + } else { + puts(cmdtp->usage); + return 1; + } + + while (1) ; /* Not reached */ + + } else if (strcmp(argv[2], "wd") == 0) { + /* + * Reset from alternate bank without changing + * frequencies but with watchdog timer enabled: + * altbank wd + */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + puts("Enabling watchdog timer on the FPGA\n"); + puts("Resetting board to boot from the other bank.\n"); + set_px_go_with_watchdog(); + while (1) ; /* Not reached */ + + } else { + puts(cmdtp->usage); + return 1; + } + + } else { + puts(cmdtp->usage); + return 1; + } + + return 0; +} + + +U_BOOT_CMD( + pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd, + "pixis_reset - Reset the board using the FPGA sequencer\n", + " pixis_reset\n" + " pixis_reset [altbank]\n" + " pixis_reset altbank wd\n" + " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" + " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" + ); diff --git a/board/mpc8641hpcn/pixis.h b/board/freescale/common/pixis.h index cd9a45db87..ff62a62c74 100644 --- a/board/mpc8641hpcn/pixis.h +++ b/board/freescale/common/pixis.h @@ -20,6 +20,7 @@ * MA 02111-1307 USA */ +extern void pixis_reset(void); extern int set_px_sysclk(ulong sysclk); extern int set_px_mpxpll(ulong mpxpll); extern int set_px_corepll(ulong corepll); @@ -28,6 +29,3 @@ extern void read_from_px_regs_altbank(int set); extern void set_altbank(void); extern void set_px_go(void); extern void set_px_go_with_watchdog(void); -extern int disable_watchdog(cmd_tbl_t *cmdtp, - int flag, int argc, char *argv[]); -extern ulong strfractoint(uchar *strptr); diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c index 98b86d1834..726366ddf0 100644 --- a/board/mcc200/lcd.c +++ b/board/mcc200/lcd.c @@ -180,10 +180,6 @@ void lcd_enable (void) break; udelay (PSOC_WAIT_TIME); } - if (!retries) { - printf ("%s Warning: PSoC doesn't respond on " - "RTS NEGATE\n", __FUNCTION__); - } return; } diff --git a/board/mpc7448hpc2/Makefile b/board/mpc7448hpc2/Makefile new file mode 100644 index 0000000000..e3d757d5dd --- /dev/null +++ b/board/mpc7448hpc2/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o tsi108_init.o +SOBJS := asm_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +.PHONY: distclean +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude ($obj).depend + +######################################################################### diff --git a/board/mpc7448hpc2/asm_init.S b/board/mpc7448hpc2/asm_init.S new file mode 100644 index 0000000000..a7a40a134c --- /dev/null +++ b/board/mpc7448hpc2/asm_init.S @@ -0,0 +1,918 @@ +/* + * (C) Copyright 2004-05; Tundra Semiconductor Corp. + * + * Added automatic detect of SDC settings + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * Maintainer tie-fei.zang@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * FILENAME: asm_init.s + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + * + */ + +#include <config.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> + +#include <tsi108.h> + +/* + * Build Configuration Options + */ + +/* #define DISABLE_PBM disables usage of PB Master */ +/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ +/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ + +/* + * Hardcoded SDC settings + */ + +#ifdef SDC_HARDCODED_INIT + +/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ + +#define VAL_SD_REFRESH (0x61A) +#define VAL_SD_TIMING (0x0308336b) +#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ +#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ + +#endif /* SDC_HARDCODED_INIT */ + +/* + CPU Configuration: + + CPU Address and Data Parity enables. + +#define CPU_AP +#define CPU_DP +*/ + +/* + * Macros + * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are + * expected to work correctly for the CSR space within 32KB range. + * + * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. + * These macros are absolutely identical except their names. This difference + * is provided intentionally for better readable code. + */ + +#define LOAD_PTR(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +#define LOAD_U32(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +/* LOADMEM initializes a register with the contents of a specified 32-bit + * memory location, usually a CSR value. + */ + +#define LOAD_MEM(reg,addr32) \ + addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) + +#ifndef SDC_HARDCODED_INIT +sdc_clk_sync: + /* MHz: 0,0,183,100,133,167,200,233 */ + .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ +#endif + +/* + * board_asm_init() - early initialization function. Coded to be portable to + * dual-CPU configuration. + * Checks CPU number and performs board HW initialization if called for CPU0. + * Registers used: r3,r4,r5,r6,r19,r29 + * + * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 + * and the rest of the board. Current implementation demonstrates two + * possible ways to identify CPU number: + * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. + * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. + */ + + .globl board_asm_init +board_asm_init: + mflr r19 /* Save LR to be able return later. */ + bl icache_enable /* Enable icache to reduce reads from flash. */ + +/* Initialize pointer to Tsi108 register space */ + + LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + ori r4,r29,TSI108_PB_REG_OFFSET + +/* Check Processor Version Number */ + + mfspr r3, PVR + rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ + + cmpli 0,0,r3,0x8000 /* MPC74xx */ + bne cont_brd_init + + /* + * For MPC744x/5x enable extended BATs[4-7] + * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 + * to disable prefetch + */ + + mfspr r5, HID0 + oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ + ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ + mtspr HID0, r5 + isync + sync + + /* Adding code to disable external interventions in MPX bus mode */ + mfspr r3, 1014 + oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ + mtspr 1014, r3 + isync + sync + + /* Sri: code to enable FP unit */ + mfmsr r3 + ori r3, r3, 0x2000 + mtmsr r3 + isync + sync + + /* def CONFIG_DUAL_CPU + * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. + */ +#if(1) + mfspr r3,1014 /* read MSSCR0 */ + rlwinm. r3,r3,27,31,31 /* get processor ID number */ + mtspr SPRN_PIR,r3 /* Save CPU ID */ + sync + bne init_done + b do_tsi108_init + +cont_brd_init: + + /* An alternative method of checking the processor number (in addition + * to configuration using MSSCR0[ID] bit on MPC74xx). + * Good for IBM PPC750FX/GX. + */ + + lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ + rlwinm. r3,r3,24,31,31 /* get processor ID number */ + bne init_done +#else + +cont_brd_init: + +#endif /* CONFIG_DUAL_CPU */ + + /* Initialize Tsi108 chip */ + +do_tsi108_init: + + /* + * Adjust HLP/Flash parameters. By default after reset the HLP port is + * set to support slow devices. Better performance can be achived when + * an optimal parameters are used for specific EPROM device. + * NOTE: This should be performed ASAP for the emulation platform + * because it has 5MHz HLP clocking. + */ + +#ifdef CONFIG_TSI108EMU + ori r4,r29,TSI108_HLP_REG_OFFSET + LOAD_U32(r5,0x434422c0) + stw r5,0x08(r4) /* set HLP B0_CTRL0 */ + sync + LOAD_U32(r5,0xd0012000) + stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ + sync +#endif + + /* Initialize PB interface. */ + + ori r4,r29,TSI108_PB_REG_OFFSET + +#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) + /* Relocate (if required) Tsi108 registers. Set new value for + * PB_REG_BAR: + * Note we are in the 32-bit address mode. + */ + LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ + stw r5,PB_REG_BAR(r4) + andis. r29,r5,0xFFFF + sync + ori r4,r29,TSI108_PB_REG_OFFSET +#endif + + /* Set PB Slave configuration register */ + + LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ + lwz r3, PB_RSR(r4) /* get PB bus mode */ + xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ + rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ + stw r5,PB_SCR(r4) + sync + + /* Configure PB Arbiter */ + + lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ +#ifdef DISABLE_PBM + ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ +#endif + andc r5,r5,r3 /* Clear the masked bit fields */ + ori r5,r5,0x0001 /* Set pipeline depth */ + stw r5,PB_ARB_CTRL(r4) + +#if (0) /* currently using the default settings for PBM after reset */ + LOAD_U32(r5,0x) /* value for PB_MCR */ + stw r5,PB_MCR(r4) + sync + + LOAD_U32(r5,0x) /* value for PB_MCMD */ + stw r5,PB_MCMD(r4) + sync +#endif + + /* Disable or enable PVT based on processor bus frequency + * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 + * 2. See if the value is < or > 133mhz (18:16 = 100) + * 3. If > enable PVT + */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,16,29,31 + + cmpi 0,0,r3,0x0004 + bgt sdc_init + +#ifndef CONFIG_TSI108EMU + /* FIXME: Disable PB calibration control for any real Tsi108 board */ + li r5,0x0101 /* disable calibration control */ + stw r5,PB_PVT_CTRL2(r4) + sync +#endif + + /* Initialize SDRAM controller. */ + +sdc_init: + +#ifndef SDC_HARDCODED_INIT + /* get SDC clock prior doing sdram controller autoconfig */ + ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ + lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ + rlwinm r3,r3,12,29,31 /* r3 - SD clk */ + lis r5,sdc_clk_sync@h + ori r5,r5,sdc_clk_sync@l + /* Sri: At this point check if r3 = 001. If yes, + * the memory frequency should be same as the + * MPX bus frequency + */ + cmpi 0,0,r3,0x0001 + bne get_nsec + lwz r6, CG_PWRUP_STATUS(r4) + rlwinm r6,r6,16,29,31 + mr r3,r6 + +get_nsec: + rlwinm r3,r3,2,0,31 + lwzx r9,r5,r3 /* get SD clk rate in nSec */ + /* ATTN: r9 will be used by SPD routine */ +#endif /* !SDC_HARDCODED_INIT */ + + ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ + + /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ + + LOAD_U32(r5,0x00) + stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ +#ifdef ENABLE_SDRAM_ECC + li r5, 0x01 +#endif /* ENABLE_SDRAM_ECC */ + stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ + sync + +#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ + + /* First read the CG_PWRUP_STATUS register to get the + * memory speed from bits 22,21,20 + */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,12,29,31 + + /* Now first check for 166, then 200, or default */ + + cmpi 0,0,r3,0x0005 + bne check_for_200mhz + + /* set values for 166 Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x00000515) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03073368) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +check_for_200mhz: + + cmpi 0,0,r3,0x0006 + bne set_default_values + + /* set values for 200Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x0000061a) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03083348) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +set_default_values: + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,VAL_SD_REFRESH) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,VAL_SD_TIMING) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync +#else /* !SDC_HARDCODED_INIT */ + bl tsi108_sdram_spd /* automatically detect SDC settings */ +#endif /* SDC_HARDCODED_INIT */ + +sdc_init_done: + +#ifdef DISABLE_PBM + LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ +#else + LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_TSI108EMU + oris r5,r5,0x0010 /* set EMULATION_MODE bit */ +#endif + + stw r5,SD_CTRL(r4) + eieio + sync + + /* Enable SDRAM access */ + + oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ + stw r5,SD_CTRL(r4) + sync + +wait_init_complete: + lwz r5,SD_STATUS(r4) + andi. r5,r5,0x0001 + /* wait until SDRAM initialization is complete */ + beq wait_init_complete + + /* Map SDRAM into the processor bus address space */ + + ori r4,r29,TSI108_PB_REG_OFFSET + + /* Setup BARs associated with direct path PB<->SDRAM */ + + /* PB_SDRAM_BAR1: + * provides a direct path to the main system memory (cacheable SDRAM) + */ + + /* BA=0,Size=512MB, ENable, No Addr.Translation */ + LOAD_U32(r5, 0x00000011) + stw r5,PB_SDRAM_BAR1(r4) + sync + + /* Make sure that PB_SDRAM_BAR1 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR1(r4) + sync + + /* PB_SDRAM_BAR2: + * provides non-cacheable alias (via the direct path) to main + * system memory. + * Size = 512MB, ENable, Addr.Translation - ON, + * BA = 0x0_40000000, TA = 0x0_00000000 + */ + + LOAD_U32(r5, 0x40010011) + stw r5,PB_SDRAM_BAR2(r4) + sync + + /* Make sure that PB_SDRAM_BAR2 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR2(r4) + sync + +init_done: + + /* All done. Restore LR and return. */ + mtlr r19 + blr + +#if (0) + /* + * init_cpu1 + * This routine enables CPU1 on the dual-processor system. + * Now there is only one processor in the system + */ + + .global enable_cpu1 +enable_cpu1: + + lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ + addi r3,r3,Tsi108_Base@l + lwz r3,0(r3) /* R3 = CSR Base Addr */ + ori r4,r3,TSI108_PB_REG_OFFSET + lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + ori r3,r3,0x0200 /* Set M1_EN bit */ + stw r3,PB_ARB_CTRL(r4) + + blr +#endif + + /* + * enable_EI + * Enable CPU core external interrupt + */ + + .global enable_EI +enable_EI: + mfmsr r3 + ori r3,r3,0x8000 /* set EE bit */ + mtmsr r3 + blr + + /* + * disable_EI + * Disable CPU core external interrupt + */ + + .global disable_EI +disable_EI: + mfmsr r3 + li r4,-32768 /* aka "li r4,0x8000" */ + andc r3,r3,r4 /* clear EE bit */ + mtmsr r3 + blr + +#ifdef ENABLE_SDRAM_ECC + /* enables SDRAM ECC */ + + .global enable_ECC +enable_ECC: + ori r4,r29,TSI108_SD_REG_OFFSET + lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ + ori r3,r3,0x0001 /* Set ECC_EN bit */ + stw r3,SD_ECC_CTRL(r4) + blr + + /* + * clear_ECC_err + * Clears all pending SDRAM ECC errors + * (normally after SDRAM scrubbing/initialization) + */ + + .global clear_ECC_err +clear_ECC_err: + ori r4,r29,TSI108_SD_REG_OFFSET + ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ + stw r3,SD_INT_STATUS(r4) + blr + +#endif /* ENABLE_SDRAM_ECC */ + +#ifndef SDC_HARDCODED_INIT + + /* SDRAM SPD Support */ +#define SD_I2C_CTRL1 (0x400) +#define SD_I2C_CTRL2 (0x404) +#define SD_I2C_RD_DATA (0x408) +#define SD_I2C_WR_DATA (0x40C) + + /* + * SDRAM SPD Support Macros + */ + +#define SPD_DIMM0 (0x00000100) +#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ + +#define SPD_RDIMM (0x01) +#define SPD_UDIMM (0x02) + +#define SPD_CAS_3 0x8 +#define SPD_CAS_4 0x10 +#define SPD_CAS_5 0x20 + +#define ERR_NO_DIMM_FOUND (0xdb0) +#define ERR_TRAS_FAIL (0xdb1) +#define ERR_TRCD_FAIL (0xdb2) +#define ERR_TRP_FAIL (0xdb3) +#define ERR_TWR_FAIL (0xdb4) +#define ERR_UNKNOWN_PART (0xdb5) +#define ERR_NRANK_INVALID (0xdb6) +#define ERR_DIMM_SIZE (0xdb7) +#define ERR_ADDR_MODE (0xdb8) +#define ERR_RFRSH_RATE (0xdb9) +#define ERR_DIMM_TYPE (0xdba) +#define ERR_CL_VALUE (0xdbb) +#define ERR_TRFC_FAIL (0xdbc) + +/* READ_SPD requirements: + * byte - byte address in SPD device (0 - 255) + * r3 = will return data read from I2C Byte location + * r4 - unchanged (SDC base addr) + * r5 - clobbered in routine (I2C status) + * r10 - number of DDR slot where first SPD device is detected + */ + +#define READ_SPD(byte_num) \ + addis r3, 0, byte_num@l; \ + or r3, r3, r10; \ + ori r3, r3, 0x0A; \ + stw r3, SD_I2C_CTRL1(r4); \ + li r3, I2C_CNTRL2_START; \ + stw r3, SD_I2C_CTRL2(r4); \ + eieio; \ + sync; \ + li r3, 0x100; \ +1:; \ + addic. r3, r3, -1; \ + bne 1b; \ +2:; \ + lwz r5, SD_I2C_CTRL2(r4); \ + rlwinm. r3,r5,0,23,23; \ + bne 2b; \ + rlwinm. r3,r5,0,3,3; \ + lwz r3,SD_I2C_RD_DATA(r4) + +#define SPD_MIN_RFRSH (0x80) +#define SPD_MAX_RFRSH (0x85) + +refresh_rates: /* in nSec */ + .long 15625 /* Normal (0x80) */ + .long 3900 /* Reduced 0.25x (0x81) */ + .long 7800 /* Reduced 0.5x (0x82) */ + .long 31300 /* Extended 2x (0x83) */ + .long 62500 /* Extended 4x (0x84) */ + .long 125000 /* Extended 8x (0x85) */ + +/* + * tsi108_sdram_spd + * + * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data + * Uses registers: r4 - SDC base address (not changed) + * r9 - SDC clocking period in nSec + * Changes registers: r3,r5,r6,r7,r8,r10,r11 + */ + +tsi108_sdram_spd: + + li r10,SPD_DIMM0 + xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ + +do_first_dimm: + + /* Program Refresh Rate Register */ + + READ_SPD(12) /* get Refresh Rate */ + beq check_next_slot + li r5, ERR_RFRSH_RATE + cmpi 0,0,r3,SPD_MIN_RFRSH + ble spd_fail + cmpi 0,0,r3,SPD_MAX_RFRSH + bgt spd_fail + addi r3,r3,-SPD_MIN_RFRSH + rlwinm r3,r3,2,0,31 + lis r5,refresh_rates@h + ori r5,r5,refresh_rates@l + lwzx r5,r5,r3 /* get refresh rate in nSec */ + divwu r5,r5,r9 /* calculate # of SDC clocks */ + stw r5,SD_REFRESH(r4) /* Set refresh rate */ + sync + + /* Program SD Timing Register */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ + beq spd_read_fail + li r5, ERR_DIMM_TYPE + cmpi 0,0,r3,SPD_UDIMM + beq do_cl + cmpi 0,0,r3,SPD_RDIMM + bne spd_fail + oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ + +do_cl: + READ_SPD(18) /* Get CAS Latency */ + beq spd_read_fail + li r5,ERR_CL_VALUE + andi. r6,r3,SPD_CAS_3 + beq cl_4 + li r6,3 + b set_cl +cl_4: + andi. r6,r3,SPD_CAS_4 + beq cl_5 + li r6,4 + b set_cl +cl_5: + andi. r6,r3,SPD_CAS_5 + beq spd_fail + li r6,5 +set_cl: + rlwimi r7,r6,24,5,7 + + READ_SPD(30) /* Get tRAS */ + beq spd_read_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_tras + addi r6,r6,1 +set_tras: + li r5,ERR_TRAS_FAIL + cmpi 0,0,r6,0x0F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,16,12,15 + + READ_SPD(29) /* Get tRCD */ + beq spd_read_fail + /* right shift tRCD by 2 bits as per DDR2 spec */ + rlwinm r3,r3,30,2,31 + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trcd + addi r6,r6,1 +set_trcd: + li r5,ERR_TRCD_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,12,17,19 + + READ_SPD(27) /* Get tRP value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trp + addi r6,r6,1 +set_trp: + li r5,ERR_TRP_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,8,21,23 + + READ_SPD(36) /* Get tWR value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_twr + addi r6,r6,1 +set_twr: + addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ + li r5,ERR_TWR_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,5,24,26 + + READ_SPD(42) /* Get tRFC */ + beq spd_read_fail + li r5, ERR_TRFC_FAIL + /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ + addi r3,r3,1 + rlwinm. r3,r3,31,1,31 /* divide by 2 */ + beq spd_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trfc + addi r6,r6,1 +set_trfc: + cmpi 0,0,r6,0x1F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,0,27,31 + + stw r7,SD_TIMING(r4) + sync + + /* + * The following two registers are set on per-DIMM basis. + * The SD_REFRESH and SD_TIMING settings are common for both DIMMS + */ + +do_each_dimm: + + /* Program SDRAM DIMM Control Register */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(13) /* Get Primary SDRAM Width */ + beq spd_read_fail + cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ + beq do_nbank + oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ + +do_nbank: + READ_SPD(17) /* Get Number of banks on SDRAM device */ + beq spd_read_fail + /* Grendel only distinguish betw. 4 or 8-bank memory parts */ + li r5,ERR_UNKNOWN_PART /* non-supported memory part */ + cmpi 0,0,r3,4 + beq do_nrank + cmpi 0,0,r3,8 + bne spd_fail + ori r7,r7,0x1000 + +do_nrank: + READ_SPD(5) /* Get # of Ranks */ + beq spd_read_fail + li r5,ERR_NRANK_INVALID + andi. r6,r3,0x7 /* Use bits [2..0] only */ + beq do_addr_mode + cmpi 0,0,r6,1 + bgt spd_fail + rlwimi r7,r6,8,23,23 + +do_addr_mode: + READ_SPD(4) /* Get # of Column Addresses */ + beq spd_read_fail + li r5, ERR_ADDR_MODE + andi. r3,r3,0x0f /* cut off reserved bits */ + cmpi 0,0,r3,8 + ble spd_fail + cmpi 0,0,r3,15 + bgt spd_fail + addi r6,r3,-8 /* calculate ADDR_MODE parameter */ + rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ + +set_dimm_ctrl: +#ifdef SDC_AUTOPRECH_EN + oris r7,r7,0x0001 /* set auto precharge EN bit */ +#endif + ori r7,r7,1 /* set ENABLE bit */ + cmpi 0,0,r10,SPD_DIMM0 + bne 1f + stw r7,SD_D0_CTRL(r4) + sync + b set_dimm_bar +1: + stw r7,SD_D1_CTRL(r4) + sync + + + /* Program SDRAM DIMMx Base Address Register */ + +set_dimm_bar: + READ_SPD(5) /* get # of Ranks */ + beq spd_read_fail + andi. r7,r3,0x7 + addi r7,r7,1 + READ_SPD(31) /* Read DIMM rank density */ + beq spd_read_fail + rlwinm r5,r3,27,29,31 + rlwinm r6,r3,3,24,28 + or r5,r6,r5 /* r5 = Normalized Rank Density byte */ + lis r8, 0x0080 /* 128MB >> 4 */ + mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ + mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ + neg r7,r8 + rlwinm r7,r7,28,4,31 + or r7,r7,r11 /* set ADDR field */ + rlwinm r8,r8,12,20,31 + add r11,r11,r8 /* set Base Addr for next DIMM */ + + cmpi 0,0,r10,SPD_DIMM0 + bne set_dimm1_size + stw r7,SD_D0_BAR(r4) + sync + li r10,SPD_DIMM1 + READ_SPD(0) + bne do_each_dimm + b spd_done + +set_dimm1_size: + stw r7,SD_D1_BAR(r4) + sync +spd_done: + blr + +check_next_slot: + cmpi 0,0,r10,SPD_DIMM1 + beq spd_read_fail + li r10,SPD_DIMM1 + b do_first_dimm +spd_read_fail: + ori r3,r0,0xdead + b err_hung +spd_fail: + li r3,0x0bad + sync +err_hung: /* hang here for debugging */ + nop + nop + b err_hung + +#endif /* !SDC_HARDCODED_INIT */ diff --git a/board/mpc7448hpc2/config.mk b/board/mpc7448hpc2/config.mk new file mode 100644 index 0000000000..2e58858c4f --- /dev/null +++ b/board/mpc7448hpc2/config.mk @@ -0,0 +1,28 @@ +# +# Copyright (c) 2005 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Flash address +TEXT_BASE = 0xFF000000 +# RAM address +#TEXT_BASE = 0x00400000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c new file mode 100644 index 0000000000..63c99de175 --- /dev/null +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2005 Freescale Semiconductor, Inc. + * + * Roy Zang <tie-fei.zang@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the Tsi108 Emul Board by avb@Tundra + */ + +/* + * board support/init functions for the + * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). + */ + +#include <common.h> +#include <74xx_7xx.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +extern void ft_cpu_setup (void *blob, bd_t *bd); +#endif + +#undef DEBUG + +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); +extern void tsi108_init_f (void); + +int display_mem_map (void); + +void after_reloc (ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Jump to the main U-Boot board init code + */ + board_init_r ((gd_t *) gd, dest_addr); + /* NOTREACHED */ +} + +/* + * Check Board Identity: + * report board type + */ + +int checkboard (void) +{ + int l_type = 0; + + printf ("BOARD: %s\n", CFG_BOARD_NAME); + return (l_type); +} + +/* + * Read Processor ID: + * + * report calling processor number + */ + +int read_pid (void) +{ + return 0; /* we are on single CPU platform for a while */ +} + +long int dram_size (int board_type) +{ + return 0x20000000; /* 256M bytes */ +} + +long int initdram (int board_type) +{ + return dram_size (board_type); +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup (void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup (blob, bd); + + p = ft_get_prop (blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); + } +} +#endif diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c new file mode 100644 index 0000000000..8a7efef772 --- /dev/null +++ b/board/mpc7448hpc2/tsi108_init.c @@ -0,0 +1,665 @@ +/***************************************************************************** + * (C) Copyright 2003; Tundra Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + *****************************************************************************/ + +/*---------------------------------------------------------------------------- + * FILENAME: tsi108_init.c + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + *---------------------------------------------------------------------------*/ + +#include <common.h> +#include <74xx_7xx.h> +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <tsi108.h> + +extern void mpicInit (int verbose); + +/* + * Configuration Options + */ + +typedef struct { + ulong upper; + ulong lower; +} PB2OCN_LUT_ENTRY; + +PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = { + /* 0 - 7 */ + {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */ + + /* 8 - 15 */ + {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */ + + /* 16 - 23 */ + {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */ + /* 24 - 31 */ + {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */ + + {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */ + {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */ + {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */ + {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/ +}; + +#ifdef CFG_CLK_SPREAD +typedef struct { + ulong ctrl0; + ulong ctrl1; +} PLL_CTRL_SET; + +/* + * Clock Generator SPLL0 initialization values + * PLL0 configuration table for various PB_CLKO freq. + * Uses pre-calculated values for Fs = 30 kHz, D = 0.5% + * Fout depends on required PB_CLKO. Based on Fref = 33 MHz + */ + +static PLL_CTRL_SET pll0_config[8] = { + {0x00000000, 0x00000000}, /* 0: bypass */ + {0x00000000, 0x00000000}, /* 1: reserved */ + {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */ + {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */ + {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */ + {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */ + {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */ + {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */ +}; +#endif /* CFG_CLK_SPREAD */ + +/* + * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT + * (based on recommended Tsi108 reference clock 33MHz) + */ +static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; + +/* + * get_board_bus_clk () + * + * returns the bus clock in Hz. + */ +unsigned long get_board_bus_clk (void) +{ + ulong i; + + /* Detect PB clock freq. */ + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ + + return pb_clk_sel[i] * 1000000; +} + +/* + * board_early_init_f () + * + * board-specific initialization executed from flash + */ + +int board_early_init_f (void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong i; + + gd->mem_clk = 0; + i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + + CG_PWRUP_STATUS); + i = (i >> 20) & 0x07; /* Get GD PLL multiplier */ + switch (i) { + case 0: /* external clock */ + printf ("Using external clock\n"); + break; + case 1: /* system clock */ + gd->mem_clk = gd->bus_clk; + break; + case 4: /* 133 MHz */ + case 5: /* 166 MHz */ + case 6: /* 200 MHz */ + gd->mem_clk = pb_clk_sel[i] * 1000000; + break; + default: + printf ("Invalid DDR2 clock setting\n"); + return -1; + } + printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); + return 0; +} + +/* + * board_early_init_r() - Tsi108 initialization function executed right after + * relocation. Contains code that cannot be executed from flash. + */ + +int board_early_init_r (void) +{ + ulong temp, i; + ulong reg_val; + volatile ulong *reg_ptr; + + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); + + for (i = 0; i < 32; i++) { + *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ + *reg_ptr++ = 0x00; + } + + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); + + /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, + 0x80000001); + __asm__ __volatile__ ("sync"); + + /* Make sure that OCN_BAR2 decoder is set (to allow following immediate + * read from SDRAM) + */ + + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); + __asm__ __volatile__ ("sync"); + + /* + * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the + * processor bus address space. Immediately after reset LUT and address + * translation are disabled for this BAR. Now we have to initialize LUT + * and switch from the BOOT mode to the normal operation mode. + * + * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 + * and covers 512MB of address space. To allow larger aperture we also + * have to relocate register window of Tsi108 + * + * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT + * mode. + * + * initialize pointer to LUT associated with PB_OCN_BAR1 + */ + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); + + for (i = 0; i < 32; i++) { + *reg_ptr++ = pb2ocn_lut1[i].lower; + *reg_ptr++ = pb2ocn_lut1[i].upper; + } + + __asm__ __volatile__ ("sync"); + + /* Base addresses for CS0, CS1, CS2, CS3 */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, + 0x00000000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, + 0x00100000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, + 0x00200000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, + 0x00300000); + __asm__ __volatile__ ("sync"); + + /* Masks for HLP banks */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); + + /* Set CTRL0 values for banks */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); + + /* Set banks to latched mode, enabled, and other default settings */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); + + /* + * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. + * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) + */ + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, + 0xE0000011); + __asm__ __volatile__ ("sync"); + + /* Make sure that OCN_BAR2 decoder is set (to allow following + * immediate read from SDRAM) + */ + + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); + __asm__ __volatile__ ("sync"); + + /* + * SRI: At this point we have enabled the HLP banks. That means we can + * now read from the NVRAM and initialize the environment variables. + * We will over-ride the env_init called in board_init_f + * This is really a work-around because, the HLP bank 1 + * where NVRAM resides is not visible during board_init_f + * (lib_ppc/board.c) + * Alternatively, we could use the I2C EEPROM at start-up to configure + * and enable all HLP banks and not just HLP 0 as is being done for + * Taiga Rev. 2. + */ + + env_init (); + +#ifndef DISABLE_PBM + + /* + * For IBM processors we have to set Address-Only commands generated + * by PBM that are different from ones set after reset. + */ + + temp = get_cpu_type (); + + if ((CPU_750FX == temp) || (CPU_750GX == temp)) + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, + 0x00009955); +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_PCI + /* + * Initialize PCI/X block + */ + + /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_PFAB_BAR0_UPPER, 0); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, + 0xFB000001); + __asm__ __volatile__ ("sync"); + + /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ + + temp = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); + + temp &= ~0xFF00; /* Clear the BUS_NUM field */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, + temp); + + /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, + 0); + __asm__ __volatile__ ("sync"); + + /* This register is on the PCI side to interpret the address it receives + * and maps it as a IO address. + */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, + 0xFA000001); + __asm__ __volatile__ ("sync"); + + /* + * Map PCI/X Memory Space + * + * Transactions directed from OCM to PCI Memory Space are directed + * from PB to PCI + * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). + * If address remapping is required the corresponding PCI_PFAB_MEM32 + * and PCI_PFAB_PFMx register groups have to be configured. + * + * Map the path from the PCI/X bus into the system memory + * + * The memory mapped window assotiated with PCI P2O_BAR2 provides + * access to the system memory without address remapping. + * All system memory is opened for accesses initiated by PCI/X bus + * masters. + * + * Initialize LUT associated with PCI P2O_BAR2 + * + * set pointer to LUT associated with PCI P2O_BAR2 + */ + + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); + +#ifdef DISABLE_PBM + + /* In case when PBM is disabled (no HW supported cache snoopng on PB) + * P2O_BAR2 is directly mapped into the system memory without address + * translation. + */ + + reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ + *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */ + } + + /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */ + reg_val = 0x00007500; +#else + + reg_val = 0x00000002; /* Destination port = PBM */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ +/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ + *reg_ptr++ = 0x40000000; +/* offset = 16MB, address translation is enabled to allow byte swapping */ + reg_val += 0x01000000; + } + +/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */ + reg_val = 0x00007100; +#endif + + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); + + /* Set 64-bit PCI bus address for system memory + * ( 0 is the best choice for easy mapping) + */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, + 0x00000000); + __asm__ __volatile__ ("sync"); + +#ifndef DISABLE_PBM + /* + * The memory mapped window assotiated with PCI P2O_BAR3 provides + * access to the system memory using SDRAM OCN port and address + * translation. This is alternative way to access SDRAM from PCI + * required for Tsi108 emulation testing. + * All system memory is opened for accesses initiated by + * PCI/X bus masters. + * + * Initialize LUT associated with PCI P2O_BAR3 + * + * set pointer to LUT associated with PCI P2O_BAR3 + */ + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); + + reg_val = 0x00000004; /* Destination port = SDC */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ + +/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ + *reg_ptr++ = 0; + +/* offset = 16MB, address translation is enabled to allow byte swapping */ + reg_val += 0x01000000; + } + + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); + + /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ + + reg_val = + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_P2O_PAGE_SIZES); + reg_val &= ~0x00FF; + reg_val |= 0x0071; + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); + + /* Set 64-bit base PCI bus address for window (0x20000000) */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, + 0x20000000); + __asm__ __volatile__ ("sync"); + +#endif /* !DISABLE_PBM */ + +#ifdef ENABLE_PCI_CSR_BAR + /* open if required access to Tsi108 CSRs from the PCI/X bus */ + /* enable BAR0 on the PCI/X bus */ + reg_val = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); + reg_val |= 0x02; + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, + reg_val); + __asm__ __volatile__ ("sync"); + + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, + CFG_TSI108_CSR_BASE); + __asm__ __volatile__ ("sync"); + +#endif + + /* + * Finally enable PCI/X Bus Master and Memory Space access + */ + + reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); + reg_val |= 0x06; + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); + __asm__ __volatile__ ("sync"); + +#endif /* CONFIG_PCI */ + + /* + * Initialize MPIC outputs (interrupt pins): + * Interrupt routing on the Grendel Emul. Board: + * PB_INT[0] -> INT (CPU0) + * PB_INT[1] -> INT (CPU1) + * PB_INT[2] -> MCP (CPU0) + * PB_INT[3] -> MCP (CPU1) + * Set interrupt controller outputs as Level_Sensitive/Active_Low + */ + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); + __asm__ __volatile__ ("sync"); + + /* + * Ensure that Machine Check exception is enabled + * We need it to support PCI Bus probing (configuration reads) + */ + + reg_val = mfmsr (); + mtmsr(reg_val | MSR_ME); + + return 0; +} + +/* + * Needed to print out L2 cache info + * used in the misc_init_r function + */ + +unsigned long get_l2cr (void) +{ + unsigned long l2controlreg; + asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); + return l2controlreg; +} + +/* + * misc_init_r() + * + * various things to do after relocation + * + */ + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ + ulong i; + + /* Ensure that Spread-Spectrum is disabled */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); + + /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK + * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% + */ + + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x002e0044); /* D = 0.25% */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, + 0x00000039); /* BWADJ */ + + /* Initialize PLL0: CG_PB_CLKO */ + /* Detect PB clock freq. */ + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ + + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); + + /* Wait and set SSEN for both PLL0 and 1 */ + udelay (1000); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x802e0044); /* D=0.25% */ + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, + 0x80000000 | pll0_config[i].ctrl0); +#endif /* CFG_CLK_SPREAD */ + +#ifdef CFG_L2 + l2cache_enable (); +#endif + printf ("BUS: %d MHz\n", gd->bus_clk / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); + + /* + * All the information needed to print the cache details is avaiblable + * at this point i.e. above call to l2cache_enable is the very last + * thing done with regards to enabling diabling the cache. + * So this seems like a good place to print all this information + */ + + printf ("CACHE: "); + switch (get_cpu_type()) { + case CPU_7447A: + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 512KB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("\n"); + break; + + case CPU_7448: + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 1MB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + break; + default: + break; + } + return 0; +} diff --git a/board/mpc7448hpc2/u-boot.lds b/board/mpc7448hpc2/u-boot.lds new file mode 100644 index 0000000000..8f24213fc3 --- /dev/null +++ b/board/mpc7448hpc2/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8360emds/config.mk b/board/mpc8360emds/config.mk index 5801a5f178..9ace8860cf 100644 --- a/board/mpc8360emds/config.mk +++ b/board/mpc8360emds/config.mk @@ -26,8 +26,3 @@ # TEXT_BASE = 0xFE000000 - -# -# Additional board-specific libraries -# -BOARDLIBS = libfdt/libfdt.a diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index deadb5ffbe..562eb8b53a 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -664,19 +664,28 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc, #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \ && defined(CONFIG_OF_BOARD_SETUP) + +/* + * Prototypes of functions that we use. + */ +void ft_cpu_setup(void *blob, bd_t *bd); + +#ifdef CONFIG_PCI +void ft_pci_setup(void *blob, bd_t *bd); +#endif + void ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_OF_LIBFDT) int nodeoffset; - int err; int tmp[2]; nodeoffset = fdt_path_offset (fdt, "/memory"); if (nodeoffset >= 0) { tmp[0] = cpu_to_be32(bd->bi_memstart); tmp[1] = cpu_to_be32(bd->bi_memsize); - err = fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp)); + fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp)); } #else u32 *p; @@ -694,4 +703,4 @@ ft_board_setup(void *blob, bd_t *bd) #endif ft_cpu_setup(blob, bd); } -#endif +#endif /* CONFIG_OF_x */ diff --git a/board/mpc8641hpcn/Makefile b/board/mpc8641hpcn/Makefile index 4b68c36743..9625211669 100644 --- a/board/mpc8641hpcn/Makefile +++ b/board/mpc8641hpcn/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pixis.o sys_eeprom.o +COBJS := $(BOARD).o sys_eeprom.o \ + ../freescale/common/pixis.o + SOBJS := init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index b2cf4a9566..7d7e2afad3 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -1,9 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * Copyright 2006, 2007 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -25,18 +21,18 @@ */ #include <common.h> -#include <command.h> #include <pci.h> #include <asm/processor.h> #include <asm/immap_86xx.h> #include <spd.h> +#include <asm/io.h> #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> extern void ft_cpu_setup(void *blob, bd_t *bd); #endif -#include "pixis.h" +#include "../freescale/common/pixis.h" #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd) #endif -void -mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - char cmd; - ulong val; - ulong corepll; - - /* - * No args is a simple reset request. - */ - if (argc <= 1) { - out8(PIXIS_BASE + PIXIS_RST, 0); - /* not reached */ - } - - cmd = argv[1][1]; - switch (cmd) { - case 'f': /* reset with frequency changed */ - if (argc < 5) - goto my_usage; - read_from_px_regs(0); - - val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); - - corepll = strfractoint(argv[3]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); - if (val == 3) { - puts("Setting registers VCFGEN0 and VCTL\n"); - read_from_px_regs(1); - puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n"); - set_px_go(); - } else - goto my_usage; - - while (1) ; /* Not reached */ - - case 'l': - if (argv[2][1] == 'f') { - read_from_px_regs(0); - read_from_px_regs_altbank(0); - /* reset with frequency changed */ - val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); - - corepll = strfractoint(argv[4]); - val = val + set_px_corepll(corepll); - val = val + set_px_mpxpll(simple_strtoul(argv[5], - NULL, 10)); - if (val == 3) { - puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs(1); - read_from_px_regs_altbank(1); - puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n"); - set_px_go_with_watchdog(); - } else - goto my_usage; - - while (1) ; /* Not reached */ - - } else if (argv[2][1] == 'd') { - /* - * Reset from alternate bank without changing - * frequencies but with watchdog timer enabled. - */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - puts("Setting registers VCFGEN1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); - set_px_go_with_watchdog(); - while (1) ; /* Not reached */ - - } else { - /* - * Reset from next bank without changing - * frequency and without watchdog timer enabled. - */ - read_from_px_regs(0); - read_from_px_regs_altbank(0); - if (argc > 2) - goto my_usage; - puts("Setting registers VCFGNE1, VBOOT, and VCTL\n"); - set_altbank(); - read_from_px_regs_altbank(1); - puts("Resetting board to boot from the other bank....\n"); - set_px_go(); - } - - default: - goto my_usage; - } - -my_usage: - puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"); - puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n"); - puts(" reset altbank [wd]\n"); - puts("For example: reset cf 40 2.5 10\n"); - puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n"); -} - - /* * get_board_sys_clk * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ diff --git a/board/nc650/config.mk b/board/nc650/config.mk index 52c8ffe353..9d9b892600 100644 --- a/board/nc650/config.mk +++ b/board/nc650/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2006 Detlev Zundel, dzu@denx.de +# (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de # (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -27,4 +27,3 @@ # TEXT_BASE = 0x40700000 -BOARDLIBS = $(obj)drivers/nand/libnand.a diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index 8a6b5b00a9..707e4b97d1 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c @@ -177,16 +177,14 @@ long int initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); udelay (1000); diff --git a/common/Makefile b/common/Makefile index 74a6af204e..5dfd3a84a2 100644 --- a/common/Makefile +++ b/common/Makefile @@ -45,7 +45,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ env_nvram.o env_nowhere.o \ exports.o \ - flash.o fpga.o ft_build.o \ + fdt_support.o flash.o fpga.o ft_build.o \ hush.o kgdb.o lcd.o lists.o lynxkdi.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 2721216bf3..32c29e55a3 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -37,6 +37,7 @@ #if defined(CONFIG_OF_LIBFDT) #include <fdt.h> #include <libfdt.h> +#include <fdt_support.h> #endif #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> @@ -748,7 +749,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16); hdr = (image_header_t *)of_flat_tree; #if defined(CONFIG_OF_LIBFDT) - if (be32_to_cpu(fdt_magic(of_flat_tree)) == FDT_MAGIC) { + if (fdt_check_header(of_flat_tree) == 0) { #else if (*(ulong *)of_flat_tree == OF_DT_HEADER) { #endif @@ -795,7 +796,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, return; } #if defined(CONFIG_OF_LIBFDT) - if (be32_to_cpu(fdt_magic(of_flat_tree + sizeof(image_header_t))) != FDT_MAGIC) { + if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) { #else if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) { #endif @@ -836,7 +837,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, } #if defined(CONFIG_OF_LIBFDT) - if (be32_to_cpu(fdt_magic(of_data)) != FDT_MAGIC) { + if (fdt_check_header((void *)of_data) != 0) { #else if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) { #endif @@ -937,23 +938,44 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (of_data) { int err; ulong of_start, of_len; + of_len = be32_to_cpu(fdt_totalsize(of_data)); - /* provide extra 8k pad */ + /* position on a 4K boundary before the initrd/kbd */ if (initrd_start) - of_start = initrd_start - of_len - 8192; + of_start = initrd_start - of_len; else - of_start = (ulong)kbd - of_len - 8192; + of_start = (ulong)kbd - of_len; of_start &= ~(4096 - 1); /* align on page */ debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", of_data, of_data + of_len - 1, of_len, of_len); - + of_flat_tree = (char *)of_start; printf (" Loading Device Tree to %08lx, end %08lx ... ", of_start, of_start + of_len - 1); - err = fdt_open_into(of_start, of_data, of_len); + err = fdt_open_into((void *)of_start, (void *)of_data, of_len); if (err != 0) { - printf ("libfdt: %s\n", fdt_strerror(err)); + printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__); } + /* + * Add the chosen node if it doesn't exist, add the env and bd_t + * if the user wants it (the logic is in the subroutines). + */ + if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { + printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree); + return; + } +#ifdef CONFIG_OF_HAS_UBOOT_ENV + if (fdt_env(of_flat_tree) < 0) { + printf("Failed creating the /u-boot-env node, aborting.\n"); + return; + } +#endif +#ifdef CONFIG_OF_HAS_BD_T + if (fdt_bd_t(of_flat_tree) < 0) { + printf("Failed creating the /bd_t node, aborting.\n"); + return; + } +#endif } #endif #if defined(CONFIG_OF_FLAT_TREE) @@ -1004,6 +1026,24 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); /* ft_dump_blob(of_flat_tree); */ #endif +#if defined(CONFIG_OF_LIBFDT) + if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) { + printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree); + return; + } +#ifdef CONFIG_OF_HAS_UBOOT_ENV + if (fdt_env(of_flat_tree) < 0) { + printf("Failed creating the /u-boot-env node, aborting.\n"); + return; + } +#endif +#ifdef CONFIG_OF_HAS_BD_T + if (fdt_bd_t(of_flat_tree) < 0) { + printf("Failed creating the /bd_t node, aborting.\n"); + return; + } +#endif +#endif /* if defined(CONFIG_OF_LIBFDT) */ (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); #endif diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 968bade626..08fe3512d4 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -30,9 +30,11 @@ #include <linux/types.h> #ifdef CONFIG_OF_LIBFDT + #include <asm/global_data.h> #include <fdt.h> #include <libfdt.h> +#include <fdt_support.h> #define MAX_LEVEL 32 /* how deeply nested we will go */ #define SCRATCHPAD 1024 /* bytes of scratchpad memory */ @@ -53,9 +55,6 @@ static char data[SCRATCHPAD]; */ static int fdt_valid(void); static void print_data(const void *data, int len); -static int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end); -static int fdt_env(void *fdt); -static int fdt_bd_t(void *fdt); /* @@ -437,7 +436,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Create a chosen node ********************************************************************/ } else if (op == 'c') { - fdt_chosen(fdt, 0, 0); + fdt_chosen(fdt, 0, 0, 1); /******************************************************************** * Create a u-boot-env node @@ -466,25 +465,36 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static int fdt_valid(void) { + int err; + if (fdt == NULL) { - printf ("The address of the fdt is invalid.\n"); - return 0; - } - if (!fdt || (fdt_magic(fdt) != FDT_MAGIC)) { - fdt = NULL; - printf ("Unrecognized fdt: bad magic\n"); - return 0; - } - if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) { - printf ("Unsupported fdt version: $d < %d\n", - FDT_FIRST_SUPPORTED_VERSION, fdt_version(fdt)); - fdt = NULL; + printf ("The address of the fdt is invalid (NULL).\n"); return 0; } - if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) { - printf ("Unsupported fdt version: $d > %d\n", - fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION); - fdt = NULL; + + err = fdt_check_header(fdt); + if (err == 0) + return 1; /* valid */ + + if (err < 0) { + printf("libfdt: %s", fdt_strerror(err)); + /* + * Be more informative on bad version. + */ + if (err == -FDT_ERR_BADVERSION) { + if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) { + printf (" - too old, fdt $d < %d", + fdt_version(fdt), FDT_FIRST_SUPPORTED_VERSION); + fdt = NULL; + } + if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) { + printf (" - too new, fdt $d > %d", + fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION); + fdt = NULL; + } + return 0; + } + printf("\n"); return 0; } return 1; @@ -593,255 +603,6 @@ static void print_data(const void *data, int len) /********************************************************************/ -static int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end) -{ - bd_t *bd = gd->bd; - int nodeoffset; - int err; - u32 tmp; /* used to set 32 bit integer properties */ - char *str; /* used to set string properties */ - ulong clock; - - if (initrd_start && initrd_end) { - err = fdt_add_reservemap_entry(fdt, - initrd_start, initrd_end - initrd_start + 1); - if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); - return err; - } - } - - /* - * See if we already have a "chosen" node, create it if not. - */ - nodeoffset = fdt_path_offset (fdt, "/chosen"); - if (nodeoffset < 0) { - /* - * Create a new node "/chosen" (offset 0 is root level) - */ - nodeoffset = fdt_add_subnode(fdt, 0, "chosen"); - if (nodeoffset < 0) { - printf("libfdt: %s\n", fdt_strerror(nodeoffset)); - return nodeoffset; - } - } - - str = getenv("bootargs"); - if (str != NULL) { - err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } - if (initrd_start && initrd_end) { - tmp = __cpu_to_be32(initrd_start); - err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp)); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - tmp = __cpu_to_be32(initrd_end); - err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp)); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } -#ifdef OF_STDOUT_PATH - err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); -#endif - - nodeoffset = fdt_path_offset (fdt, "/cpus"); - if (nodeoffset >= 0) { - clock = cpu_to_be32(bd->bi_intfreq); - err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } -#ifdef OF_TBCLK - nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency"); - if (nodeoffset >= 0) { - clock = cpu_to_be32(OF_TBCLK); - err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } -#endif -} - -/********************************************************************/ - -#ifdef CONFIG_OF_HAS_BD_T - -/* Function that returns a character from the environment */ -extern uchar(*env_get_char) (int); - -#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) } - -static const struct { - const char *name; - int offset; -} bd_map[] = { - BDM(memstart), - BDM(memsize), - BDM(flashstart), - BDM(flashsize), - BDM(flashoffset), - BDM(sramstart), - BDM(sramsize), -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) - BDM(immr_base), -#endif -#if defined(CONFIG_MPC5xxx) - BDM(mbar_base), -#endif -#if defined(CONFIG_MPC83XX) - BDM(immrbar), -#endif -#if defined(CONFIG_MPC8220) - BDM(mbar_base), - BDM(inpfreq), - BDM(pcifreq), - BDM(pevfreq), - BDM(flbfreq), - BDM(vcofreq), -#endif - BDM(bootflags), - BDM(ip_addr), - BDM(intfreq), - BDM(busfreq), -#ifdef CONFIG_CPM2 - BDM(cpmfreq), - BDM(brgfreq), - BDM(sccfreq), - BDM(vco), -#endif -#if defined(CONFIG_MPC5xxx) - BDM(ipbfreq), - BDM(pcifreq), -#endif - BDM(baudrate), -}; - -static int fdt_env(void *fdt) -{ - int nodeoffset; - int err; - int k, nxt; - int i; - static char tmpenv[256]; - - /* - * See if we already have a "u-boot-env" node, delete it if so. - * Then create a new empty node. - */ - nodeoffset = fdt_path_offset (fdt, "/u-boot-env"); - if (nodeoffset >= 0) { - err = fdt_del_node(fdt, nodeoffset); - if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); - return err; - } - } - /* - * Create a new node "/u-boot-env" (offset 0 is root level) - */ - nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env"); - if (nodeoffset < 0) { - printf("libfdt: %s\n", fdt_strerror(nodeoffset)); - return nodeoffset; - } - - for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { - char *s, *lval, *rval; - - /* - * Find the end of the name=definition - */ - for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) - ; - s = tmpenv; - for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k) - *s++ = env_get_char(k); - *s++ = '\0'; - lval = tmpenv; - /* - * Find the first '=': it separates the name from the value - */ - s = strchr(tmpenv, '='); - if (s != NULL) { - *s++ = '\0'; - rval = s; - } else - continue; - err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1); - if (err < 0) { - printf("\"%s\" - libfdt: %s\n", lval, fdt_strerror(err)); - return err; - } - } - return 0; -} -#endif /* CONFIG_OF_HAS_UBOOT_ENV */ - -/********************************************************************/ - -#ifdef CONFIG_OF_HAS_BD_T -static int fdt_bd_t(void *fdt) -{ - bd_t *bd = gd->bd; - int nodeoffset; - int err; - u32 tmp; /* used to set 32 bit integer properties */ - int i; - - /* - * See if we already have a "bd_t" node, delete it if so. - * Then create a new empty node. - */ - nodeoffset = fdt_path_offset (fdt, "/bd_t"); - if (nodeoffset >= 0) { - err = fdt_del_node(fdt, nodeoffset); - if (err < 0) { - printf("libfdt: %s\n", fdt_strerror(err)); - return err; - } - } - /* - * Create a new node "/bd_t" (offset 0 is root level) - */ - nodeoffset = fdt_add_subnode(fdt, 0, "bd_t"); - if (nodeoffset < 0) { - printf("libfdt: %s\n", fdt_strerror(nodeoffset)); - return nodeoffset; - } - /* - * Use the string/pointer structure to create the entries... - */ - for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { - tmp = cpu_to_be32(getenv("bootargs")); - err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp)); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - } - /* - * Add a couple of oddball entries... - */ - err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4); - if (err < 0) - printf("libfdt: %s\n", fdt_strerror(err)); - -#ifdef CONFIG_OF_BOARD_SETUP - ft_board_setup(fdt, bd); -#endif - - return 0; -} -#endif /* CONFIG_OF_HAS_BD_T */ - -/********************************************************************/ - U_BOOT_CMD( fdt, 5, 0, do_fdt, "fdt - flattened device tree utility commands\n", @@ -871,4 +632,4 @@ U_BOOT_CMD( " fdt set /cpus \"#address-cells\" \"[00 00 00 01]\"\n" ); -#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_OF_LIBFDT */ diff --git a/common/fdt_support.c b/common/fdt_support.c new file mode 100644 index 0000000000..69099c4275 --- /dev/null +++ b/common/fdt_support.c @@ -0,0 +1,347 @@ +/* + * (C) Copyright 2007 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/ctype.h> +#include <linux/types.h> + +#ifdef CONFIG_OF_LIBFDT + +#include <asm/global_data.h> +#include <fdt.h> +#include <libfdt.h> +#include <fdt_support.h> + +/* + * Global data (for the gd->bd) + */ +DECLARE_GLOBAL_DATA_PTR; + + +/********************************************************************/ + +int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force) +{ + bd_t *bd = gd->bd; + int nodeoffset; + int err; + u32 tmp; /* used to set 32 bit integer properties */ + char *str; /* used to set string properties */ + ulong clock; + + err = fdt_check_header(fdt); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + + if (initrd_start && initrd_end) { + struct fdt_reserve_entry re; + int used; + int total; + int j; + + err = fdt_num_reservemap(fdt, &used, &total); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + if (used >= total) { + printf("fdt_chosen: no room in the reserved map (%d of %d)\n", + used, total); + return -1; + } + /* + * Look for an existing entry and update it. If we don't find + * the entry, we will j be the next available slot. + */ + for (j = 0; j < used; j++) { + err = fdt_get_reservemap(fdt, j, &re); + if (re.address == initrd_start) { + break; + } + } + err = fdt_replace_reservemap_entry(fdt, j, + initrd_start, initrd_end - initrd_start + 1); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + } + + /* + * Find the "chosen" node. + */ + nodeoffset = fdt_path_offset (fdt, "/chosen"); + + /* + * If we have a "chosen" node already the "force the writing" + * is not set, our job is done. + */ + if ((nodeoffset >= 0) && !force) + return 0; + + /* + * No "chosen" node in the blob: create it. + */ + if (nodeoffset < 0) { + /* + * Create a new node "/chosen" (offset 0 is root level) + */ + nodeoffset = fdt_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) { + printf("libfdt: %s\n", fdt_strerror(nodeoffset)); + return nodeoffset; + } + } + + /* + * Update pre-existing properties, create them if non-existant. + */ + str = getenv("bootargs"); + if (str != NULL) { + err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + } + if (initrd_start && initrd_end) { + tmp = __cpu_to_be32(initrd_start); + err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp)); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + tmp = __cpu_to_be32(initrd_end); + err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp)); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + } +#ifdef OF_STDOUT_PATH + err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); +#endif + + nodeoffset = fdt_path_offset (fdt, "/cpus"); + if (nodeoffset >= 0) { + clock = cpu_to_be32(bd->bi_intfreq); + err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + } +#ifdef OF_TBCLK + nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency"); + if (nodeoffset >= 0) { + clock = cpu_to_be32(OF_TBCLK); + err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + } +#endif + return err; +} + +/********************************************************************/ + +#ifdef CONFIG_OF_HAS_UBOOT_ENV + +/* Function that returns a character from the environment */ +extern uchar(*env_get_char) (int); + + +int fdt_env(void *fdt) +{ + int nodeoffset; + int err; + int k, nxt; + int i; + static char tmpenv[256]; + + err = fdt_check_header(fdt); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + + /* + * See if we already have a "u-boot-env" node, delete it if so. + * Then create a new empty node. + */ + nodeoffset = fdt_path_offset (fdt, "/u-boot-env"); + if (nodeoffset >= 0) { + err = fdt_del_node(fdt, nodeoffset); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + } + /* + * Create a new node "/u-boot-env" (offset 0 is root level) + */ + nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env"); + if (nodeoffset < 0) { + printf("libfdt: %s\n", fdt_strerror(nodeoffset)); + return nodeoffset; + } + + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + char *s, *lval, *rval; + + /* + * Find the end of the name=definition + */ + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) + ; + s = tmpenv; + for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k) + *s++ = env_get_char(k); + *s++ = '\0'; + lval = tmpenv; + /* + * Find the first '=': it separates the name from the value + */ + s = strchr(tmpenv, '='); + if (s != NULL) { + *s++ = '\0'; + rval = s; + } else + continue; + err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + } + return 0; +} +#endif /* ifdef CONFIG_OF_HAS_UBOOT_ENV */ + +/********************************************************************/ + +#ifdef CONFIG_OF_HAS_BD_T + +#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) } + +static const struct { + const char *name; + int offset; +} bd_map[] = { + BDM(memstart), + BDM(memsize), + BDM(flashstart), + BDM(flashsize), + BDM(flashoffset), + BDM(sramstart), + BDM(sramsize), +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) + BDM(immr_base), +#endif +#if defined(CONFIG_MPC5xxx) + BDM(mbar_base), +#endif +#if defined(CONFIG_MPC83XX) + BDM(immrbar), +#endif +#if defined(CONFIG_MPC8220) + BDM(mbar_base), + BDM(inpfreq), + BDM(pcifreq), + BDM(pevfreq), + BDM(flbfreq), + BDM(vcofreq), +#endif + BDM(bootflags), + BDM(ip_addr), + BDM(intfreq), + BDM(busfreq), +#ifdef CONFIG_CPM2 + BDM(cpmfreq), + BDM(brgfreq), + BDM(sccfreq), + BDM(vco), +#endif +#if defined(CONFIG_MPC5xxx) + BDM(ipbfreq), + BDM(pcifreq), +#endif + BDM(baudrate), +}; + + +int fdt_bd_t(void *fdt) +{ + bd_t *bd = gd->bd; + int nodeoffset; + int err; + u32 tmp; /* used to set 32 bit integer properties */ + int i; + + err = fdt_check_header(fdt); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + + /* + * See if we already have a "bd_t" node, delete it if so. + * Then create a new empty node. + */ + nodeoffset = fdt_path_offset (fdt, "/bd_t"); + if (nodeoffset >= 0) { + err = fdt_del_node(fdt, nodeoffset); + if (err < 0) { + printf("libfdt: %s\n", fdt_strerror(err)); + return err; + } + } + /* + * Create a new node "/bd_t" (offset 0 is root level) + */ + nodeoffset = fdt_add_subnode(fdt, 0, "bd_t"); + if (nodeoffset < 0) { + printf("libfdt: %s\n", fdt_strerror(nodeoffset)); + return nodeoffset; + } + /* + * Use the string/pointer structure to create the entries... + */ + for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { + tmp = cpu_to_be32(getenv("bootargs")); + err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp)); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + } + /* + * Add a couple of oddball entries... + */ + err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4); + if (err < 0) + printf("libfdt: %s\n", fdt_strerror(err)); + + return 0; +} +#endif /* ifdef CONFIG_OF_HAS_BD_T */ + +#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index f4e5fc504b..9c8998b604 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -44,6 +44,10 @@ #include <74xx_7xx.h> #include <asm/cache.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include <ft_build.h> +#endif + #ifdef CONFIG_AMIGAONEG3SE #include "../board/MAI/AmigaOneG3SE/via686.h" #include "../board/MAI/AmigaOneG3SE/memio.h" @@ -101,6 +105,10 @@ get_cpu_type(void) type = CPU_7457; break; + case 0x8003: + type = CPU_7447A; + break; + case 0x8004: type = CPU_7448; break; @@ -156,6 +164,10 @@ int checkcpu (void) str = "MPC7410"; break; + case CPU_7447A: + str = "MPC7447A"; + break; + case CPU_7448: str = "MPC7448"; break; @@ -264,20 +276,19 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * For the 7400 the TB clock runs at 1/4 the cpu bus speed. */ -#ifdef CONFIG_AMIGAONEG3SE +#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK) unsigned long get_tbclk(void) { return (gd->bus_clk / 4); } -#else /* ! CONFIG_AMIGAONEG3SE */ +#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/ unsigned long get_tbclk (void) { return CFG_BUS_HZ / 4; } -#endif /* CONFIG_AMIGAONEG3SE */ +#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/ /* ------------------------------------------------------------------------- */ - #if defined(CONFIG_WATCHDOG) #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) void @@ -289,3 +300,30 @@ watchdog_reset(void) #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_cpu_setup (void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + + clock = bd->bi_busfreq; + + p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32 (clock); + +#if defined(CONFIG_TSI108_ETH) + p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len); + memcpy (p, bd->bi_enetaddr, 6); +#endif + +#if defined(CONFIG_HAS_ETH1) + p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len); + memcpy (p, bd->bi_enet1addr, 6); +#endif +} +#endif +/* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c index e02a4cc21c..1dd1b2cd84 100644 --- a/cpu/74xx_7xx/cpu_init.c +++ b/cpu/74xx_7xx/cpu_init.c @@ -43,6 +43,7 @@ cpu_init_f (void) case CPU_7450: case CPU_7455: case CPU_7457: + case CPU_7447A: case CPU_7448: /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index d1800ede05..d8c40cea01 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -31,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern unsigned long get_board_bus_clk (void); + static const int hid1_multipliers_x_10[] = { 25, /* 0000 - 2.5x */ 75, /* 0001 - 7.5x */ @@ -50,6 +52,42 @@ static const int hid1_multipliers_x_10[] = { 0 /* 1111 - off */ }; +/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */ +static const int hid1_74xx_multipliers_x_10[] = { + 115, /* 00000 - 11.5x */ + 170, /* 00001 - 17x */ + 75, /* 00010 - 7.5x */ + 150, /* 00011 - 15x */ + 70, /* 00100 - 7x */ + 180, /* 00101 - 18x */ + 10, /* 00110 - bypass */ + 200, /* 00111 - 20x */ + 20, /* 01000 - 2x */ + 210, /* 01001 - 21x */ + 65, /* 01010 - 6.5x */ + 130, /* 01011 - 13x */ + 85, /* 01100 - 8.5x */ + 240, /* 01101 - 24x */ + 95, /* 01110 - 9.5x */ + 90, /* 01111 - 9x */ + 30, /* 10000 - 3x */ + 105, /* 10001 - 10.5x */ + 55, /* 10010 - 5.5x */ + 110, /* 10011 - 11x */ + 40, /* 10100 - 4x */ + 100, /* 10101 - 10x */ + 50, /* 10110 - 5x */ + 120, /* 10111 - 12x */ + 80, /* 11000 - 8x */ + 140, /* 11001 - 14x */ + 60, /* 11010 - 6x */ + 160, /* 11011 - 16x */ + 135, /* 11100 - 13.5x */ + 280, /* 11101 - 28x */ + 0, /* 11110 - off */ + 125 /* 11111 - 12.5x */ +}; + static const int hid1_fx_multipliers_x_10[] = { 00, /* 0000 - off */ 00, /* 0001 - off */ @@ -89,22 +127,30 @@ int get_clocks (void) { ulong clock = 0; +#ifdef CFG_BUS_CLK + gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */ +#else + gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ +#endif + /* calculate the clock frequency based upon the CPU type */ switch (get_cpu_type()) { + case CPU_7447A: case CPU_7448: case CPU_7455: case CPU_7457: /* - * It is assumed that the PLL_EXT line is zero. * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; + clock = (gd->bus_clk / 10) * + hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; break; case CPU_750GX: case CPU_750FX: - clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; + clock = gd->bus_clk * + hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; break; case CPU_7450: @@ -121,7 +167,8 @@ int get_clocks (void) * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; + clock = (gd->bus_clk / 10) * + hid1_multipliers_x_10[get_hid1 () >> 28]; break; case CPU_UNKNOWN: @@ -131,7 +178,6 @@ int get_clocks (void) } gd->cpu_clk = clock; - gd->bus_clk = CFG_BUS_CLK; return (0); } diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index f62ec8bc9b..f69b1f3854 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a START := start.o SOBJS := entry.o COBJS := cpu.o hsdramc.o exception.o cache.o -COBJS += interrupts.o device.o pm.o pio.o +COBJS += interrupts.o pio.o atmel_mci.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/at32ap/at32ap7000/Makefile b/cpu/at32ap/at32ap7000/Makefile index 2ed74d2508..d276712118 100644 --- a/cpu/at32ap/at32ap7000/Makefile +++ b/cpu/at32ap/at32ap7000/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).a -COBJS := hebi.o devices.o +COBJS := gpio.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/at32ap/at32ap7000/devices.c b/cpu/at32ap/at32ap7000/devices.c deleted file mode 100644 index 8b216e906a..0000000000 --- a/cpu/at32ap/at32ap7000/devices.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> - -#include <asm/arch/memory-map.h> -#include <asm/arch/platform.h> - -#include "../sm.h" - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -const struct clock_domain chip_clock[] = { - [CLOCK_CPU] = { - .reg = SM_PM_CPU_MASK, - .id = CLOCK_CPU, - .bridge = NO_DEVICE, - }, - [CLOCK_HSB] = { - .reg = SM_PM_HSB_MASK, - .id = CLOCK_HSB, - .bridge = NO_DEVICE, - }, - [CLOCK_PBA] = { - .reg = SM_PM_PBA_MASK, - .id = CLOCK_PBA, - .bridge = DEVICE_PBA_BRIDGE, - }, - [CLOCK_PBB] = { - .reg = SM_PM_PBB_MASK, - .id = CLOCK_PBB, - .bridge = DEVICE_PBB_BRIDGE, - }, -}; - -static const struct resource hebi_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 0 }, - }, - }, { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 13 }, - }, - }, { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 14 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 }, - }, - }, -}; -static const struct resource pba_bridge_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 1 }, - } - }, { - .type = RESOURCE_CLOCK, - .u = { - /* HSB-HSB Bridge */ - .clock = { CLOCK_HSB, 4 }, - }, - }, -}; -static const struct resource pbb_bridge_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 2 }, - }, - }, -}; -static const struct resource hramc_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 3 }, - }, - }, -}; -static const struct resource pioa_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 10 }, - }, - }, -}; -static const struct resource piob_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 11 }, - }, - }, -}; -static const struct resource pioc_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 12 }, - }, - }, -}; -static const struct resource piod_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 13 }, - }, - }, -}; -static const struct resource pioe_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 14 }, - }, - }, -}; -static const struct resource sm_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 0 }, - }, - }, -}; -static const struct resource intc_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 1 }, - }, - }, -}; -static const struct resource hmatrix_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 2 }, - }, - }, -}; -#if defined(CFG_HPDC) -static const struct resource hpdc_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 16 }, - }, - }, -}; -#endif -#if defined(CFG_MACB0) -static const struct resource macb0_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 8 }, - }, - }, { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 6 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 }, - }, - }, -}; -#endif -#if defined(CFG_MACB1) -static const struct resource macb1_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 9 }, - }, - }, { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 7 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 }, - }, - }, -}; -#endif -#if defined(CFG_LCDC) -static const struct resource lcdc_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 7 }, - }, - }, -}; -#endif -#if defined(CFG_USART0) -static const struct resource usart0_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 3 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 }, - }, - }, -}; -#endif -#if defined(CFG_USART1) -static const struct resource usart1_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 4 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 }, - }, - }, -}; -#endif -#if defined(CFG_USART2) -static const struct resource usart2_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 5 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 }, - }, - }, -}; -#endif -#if defined(CFG_USART3) -static const struct resource usart3_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBA, 6 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 }, - }, - }, -}; -#endif -#if defined(CFG_MMCI) -static const struct resource mmci_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_PBB, 9 }, - }, - }, { - .type = RESOURCE_GPIO, - .u = { - .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 }, - }, - }, -}; -#endif -#if defined(CFG_DMAC) -static const struct resource dmac_resource[] = { - { - .type = RESOURCE_CLOCK, - .u = { - .clock = { CLOCK_HSB, 10 }, - }, - }, -}; -#endif - -const struct device chip_device[] = { - [DEVICE_HEBI] = { - .regs = (void *)HSMC_BASE, - .nr_resources = ARRAY_SIZE(hebi_resource), - .resource = hebi_resource, - }, - [DEVICE_PBA_BRIDGE] = { - .nr_resources = ARRAY_SIZE(pba_bridge_resource), - .resource = pba_bridge_resource, - }, - [DEVICE_PBB_BRIDGE] = { - .nr_resources = ARRAY_SIZE(pbb_bridge_resource), - .resource = pbb_bridge_resource, - }, - [DEVICE_HRAMC] = { - .nr_resources = ARRAY_SIZE(hramc_resource), - .resource = hramc_resource, - }, - [DEVICE_PIOA] = { - .regs = (void *)PIOA_BASE, - .nr_resources = ARRAY_SIZE(pioa_resource), - .resource = pioa_resource, - }, - [DEVICE_PIOB] = { - .regs = (void *)PIOB_BASE, - .nr_resources = ARRAY_SIZE(piob_resource), - .resource = piob_resource, - }, - [DEVICE_PIOC] = { - .regs = (void *)PIOC_BASE, - .nr_resources = ARRAY_SIZE(pioc_resource), - .resource = pioc_resource, - }, - [DEVICE_PIOD] = { - .regs = (void *)PIOD_BASE, - .nr_resources = ARRAY_SIZE(piod_resource), - .resource = piod_resource, - }, - [DEVICE_PIOE] = { - .regs = (void *)PIOE_BASE, - .nr_resources = ARRAY_SIZE(pioe_resource), - .resource = pioe_resource, - }, - [DEVICE_SM] = { - .regs = (void *)SM_BASE, - .nr_resources = ARRAY_SIZE(sm_resource), - .resource = sm_resource, - }, - [DEVICE_INTC] = { - .regs = (void *)INTC_BASE, - .nr_resources = ARRAY_SIZE(intc_resource), - .resource = intc_resource, - }, - [DEVICE_HMATRIX] = { - .regs = (void *)HMATRIX_BASE, - .nr_resources = ARRAY_SIZE(hmatrix_resource), - .resource = hmatrix_resource, - }, -#if defined(CFG_HPDC) - [DEVICE_HPDC] = { - .nr_resources = ARRAY_SIZE(hpdc_resource), - .resource = hpdc_resource, - }, -#endif -#if defined(CFG_MACB0) - [DEVICE_MACB0] = { - .regs = (void *)MACB0_BASE, - .nr_resources = ARRAY_SIZE(macb0_resource), - .resource = macb0_resource, - }, -#endif -#if defined(CFG_MACB1) - [DEVICE_MACB1] = { - .regs = (void *)MACB1_BASE, - .nr_resources = ARRAY_SIZE(macb1_resource), - .resource = macb1_resource, - }, -#endif -#if defined(CFG_LCDC) - [DEVICE_LCDC] = { - .nr_resources = ARRAY_SIZE(lcdc_resource), - .resource = lcdc_resource, - }, -#endif -#if defined(CFG_USART0) - [DEVICE_USART0] = { - .regs = (void *)USART0_BASE, - .nr_resources = ARRAY_SIZE(usart0_resource), - .resource = usart0_resource, - }, -#endif -#if defined(CFG_USART1) - [DEVICE_USART1] = { - .regs = (void *)USART1_BASE, - .nr_resources = ARRAY_SIZE(usart1_resource), - .resource = usart1_resource, - }, -#endif -#if defined(CFG_USART2) - [DEVICE_USART2] = { - .regs = (void *)USART2_BASE, - .nr_resources = ARRAY_SIZE(usart2_resource), - .resource = usart2_resource, - }, -#endif -#if defined(CFG_USART3) - [DEVICE_USART3] = { - .regs = (void *)USART3_BASE, - .nr_resources = ARRAY_SIZE(usart3_resource), - .resource = usart3_resource, - }, -#endif -#if defined(CFG_MMCI) - [DEVICE_MMCI] = { - .regs = (void *)MMCI_BASE, - .nr_resources = ARRAY_SIZE(mmci_resource), - .resource = mmci_resource, - }, -#endif -#if defined(CFG_DMAC) - [DEVICE_DMAC] = { - .regs = (void *)DMAC_BASE, - .nr_resources = ARRAY_SIZE(dmac_resource), - .resource = dmac_resource, - }, -#endif -}; diff --git a/cpu/at32ap/at32ap7000/gpio.c b/cpu/at32ap/at32ap7000/gpio.c new file mode 100644 index 0000000000..52f5372a60 --- /dev/null +++ b/cpu/at32ap/at32ap7000/gpio.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/arch/gpio.h> + +/* + * Lots of small functions here. We depend on --gc-sections getting + * rid of the ones we don't need. + */ +void gpio_enable_ebi(void) +{ +#ifdef CFG_HSDRAMC +#ifndef CFG_SDRAM_16BIT + gpio_select_periph_A(GPIO_PIN_PE0, 0); + gpio_select_periph_A(GPIO_PIN_PE1, 0); + gpio_select_periph_A(GPIO_PIN_PE2, 0); + gpio_select_periph_A(GPIO_PIN_PE3, 0); + gpio_select_periph_A(GPIO_PIN_PE4, 0); + gpio_select_periph_A(GPIO_PIN_PE5, 0); + gpio_select_periph_A(GPIO_PIN_PE6, 0); + gpio_select_periph_A(GPIO_PIN_PE7, 0); + gpio_select_periph_A(GPIO_PIN_PE8, 0); + gpio_select_periph_A(GPIO_PIN_PE9, 0); + gpio_select_periph_A(GPIO_PIN_PE10, 0); + gpio_select_periph_A(GPIO_PIN_PE11, 0); + gpio_select_periph_A(GPIO_PIN_PE12, 0); + gpio_select_periph_A(GPIO_PIN_PE13, 0); + gpio_select_periph_A(GPIO_PIN_PE14, 0); + gpio_select_periph_A(GPIO_PIN_PE15, 0); +#endif + gpio_select_periph_A(GPIO_PIN_PE26, 0); +#endif +} + +void gpio_enable_usart0(void) +{ + gpio_select_periph_B(GPIO_PIN_PA8, 0); + gpio_select_periph_B(GPIO_PIN_PA9, 0); +} + +void gpio_enable_usart1(void) +{ + gpio_select_periph_A(GPIO_PIN_PA17, 0); + gpio_select_periph_A(GPIO_PIN_PA18, 0); +} + +void gpio_enable_usart2(void) +{ + gpio_select_periph_B(GPIO_PIN_PB26, 0); + gpio_select_periph_B(GPIO_PIN_PB27, 0); +} + +void gpio_enable_usart3(void) +{ + gpio_select_periph_B(GPIO_PIN_PB18, 0); + gpio_select_periph_B(GPIO_PIN_PB19, 0); +} + +void gpio_enable_macb0(void) +{ + gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ + gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ + gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ + gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ + gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ + gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ + gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ + gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ + gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ + gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ + gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ + gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ + gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ + gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ + gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ + gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ + gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ + gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */ +#endif +} + +void gpio_enable_macb1(void) +{ + gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ + gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ + gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ + gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ + gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ + gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ + gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ + gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ + gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ + gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ + gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ + gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ + gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ + gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ + gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ + gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ + gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ + gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ +#endif +} + +void gpio_enable_mmci(void) +{ + gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ + gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */ + gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */ + gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */ + gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ + gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ +} diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c new file mode 100644 index 0000000000..9f62c0f14b --- /dev/null +++ b/cpu/at32ap/atmel_mci.c @@ -0,0 +1,477 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#ifdef CONFIG_MMC + +#include <part.h> +#include <mmc.h> + +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/byteorder.h> +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> + +#include "atmel_mci.h" + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + +#ifndef CFG_MMC_CLK_OD +#define CFG_MMC_CLK_OD 150000 +#endif + +#ifndef CFG_MMC_CLK_PP +#define CFG_MMC_CLK_PP 5000000 +#endif + +#ifndef CFG_MMC_OP_COND +#define CFG_MMC_OP_COND 0x00100000 +#endif + +#define MMC_DEFAULT_BLKLEN 512 +#define MMC_DEFAULT_RCA 1 + +static unsigned int mmc_rca; +static block_dev_desc_t mmc_blkdev; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + return &mmc_blkdev; +} + +static void mci_set_mode(unsigned long hz, unsigned long blklen) +{ + unsigned long bus_hz; + unsigned long clkdiv; + + bus_hz = get_mci_clk_rate(); + clkdiv = (bus_hz / hz) / 2 - 1; + + pr_debug("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); + + if (clkdiv & ~255UL) { + clkdiv = 255; + printf("mmc: clock %lu too low; setting CLKDIV to 255\n", + hz); + } + + blklen &= 0xfffc; + mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) + | MMCI_BF(BLKLEN, blklen))); +} + +#define RESP_NO_CRC 1 +#define R1 MMCI_BF(RSPTYP, 1) +#define R2 MMCI_BF(RSPTYP, 2) +#define R3 (R1 | RESP_NO_CRC) +#define R6 R1 +#define NID MMCI_BF(MAXLAT, 0) +#define NCR MMCI_BF(MAXLAT, 1) +#define TRCMD_START MMCI_BF(TRCMD, 1) +#define TRDIR_READ MMCI_BF(TRDIR, 1) +#define TRTYP_BLOCK MMCI_BF(TRTYP, 0) +#define INIT_CMD MMCI_BF(SPCMD, 1) +#define OPEN_DRAIN MMCI_BF(OPDCMD, 1) + +#define ERROR_FLAGS (MMCI_BIT(DTOE) \ + | MMCI_BIT(RDIRE) \ + | MMCI_BIT(RENDE) \ + | MMCI_BIT(RINDE) \ + | MMCI_BIT(RTOE)) + +static int +mmc_cmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long *response = resp; + int i, response_words = 0; + unsigned long error_flags; + u32 status; + + pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", + cmd, arg, flags); + + error_flags = ERROR_FLAGS; + if (!(flags & RESP_NO_CRC)) + error_flags |= MMCI_BIT(RCRCE); + + flags &= ~MMCI_BF(CMDNB, ~0UL); + + if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP) + response_words = 1; + else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP) + response_words = 4; + + mmci_writel(ARGR, arg); + mmci_writel(CMDR, cmd | flags); + do { + udelay(40); + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(CMDRDY))); + + pr_debug("mmc: status 0x%08lx\n", status); + + if (status & ERROR_FLAGS) { + printf("mmc: command %lu failed (status: 0x%08lx)\n", + cmd, status); + return -EIO; + } + + if (response_words) + pr_debug("mmc: response:"); + + for (i = 0; i < response_words; i++) { + response[i] = mmci_readl(RSPR); + pr_debug(" %08lx", response[i]); + } + pr_debug("\n"); + + return 0; +} + +static int mmc_acmd(unsigned long cmd, unsigned long arg, + void *resp, unsigned long flags) +{ + unsigned long aresp[4]; + int ret; + + /* + * Seems like the APP_CMD part of an ACMD has 64 cycles max + * latency even though the ACMD part doesn't. This isn't + * entirely clear in the SD Card spec, but some cards refuse + * to work if we attempt to use 5 cycles max latency here... + */ + ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, + R1 | NCR | (flags & OPEN_DRAIN)); + if (ret) + return ret; + if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD) + return -ENODEV; + + ret = mmc_cmd(cmd, arg, resp, flags); + return ret; +} + +static unsigned long +mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + u32 status; + + if (blkcnt == 0) + return 0; + + pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + + for (i = 0; i < blkcnt; i++, start++) { + ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, + start * mmc_blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_READ + | TRTYP_BLOCK)); + if (ret) goto fail; + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(SR); + if (status & (ERROR_FLAGS | MMCI_BIT(OVRE))) + goto fail; + } while (!(status & MMCI_BIT(RXRDY))); + + if (status & MMCI_BIT(RXRDY)) { + data = mmci_readl(RDR); + /* pr_debug("%x\n", data); */ + *buffer++ = data; + wordcount++; + } + } while(wordcount < (512 / 4)); + + pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(BLKE))); + + putc('.'); + } + +out: + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + return i; + +fail: + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + printf("mmc: bread failed, card status = ", card_status); + goto out; +} + +static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = resp[2] >> 24; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 16; + cid->psn = (resp[2] << 16) | (resp[3] >> 16); + cid->mdt = resp[3] >> 8; +} + +static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) +{ + cid->mid = resp[0] >> 24; + cid->oid = (resp[0] >> 8) & 0xffff; + cid->pnm[0] = resp[0]; + cid->pnm[1] = resp[1] >> 24; + cid->pnm[2] = resp[1] >> 16; + cid->pnm[3] = resp[1] >> 8; + cid->pnm[4] = resp[1]; + cid->pnm[5] = 0; + cid->pnm[6] = 0; + cid->prv = resp[2] >> 24; + cid->psn = (resp[2] << 8) | (resp[3] >> 24); + cid->mdt = (resp[3] >> 8) & 0x0fff; +} + +static void mmc_dump_cid(const struct mmc_cid *cid) +{ + printf("Manufacturer ID: %02lX\n", cid->mid); + printf("OEM/Application ID: %04lX\n", cid->oid); + printf("Product name: %s\n", cid->pnm); + printf("Product Revision: %lu.%lu\n", + cid->prv >> 4, cid->prv & 0x0f); + printf("Product Serial Number: %lu\n", cid->psn); + printf("Manufacturing Date: %02lu/%02lu\n", + cid->mdt >> 4, cid->mdt & 0x0f); +} + +static void mmc_dump_csd(const struct mmc_csd *csd) +{ + unsigned long *csd_raw = (unsigned long *)csd; + printf("CSD data: %08lx %08lx %08lx %08lx\n", + csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); + printf("CSD structure version: 1.%u\n", csd->csd_structure); + printf("MMC System Spec version: %u\n", csd->spec_vers); + printf("Card command classes: %03x\n", csd->ccc); + printf("Read block length: %u\n", 1 << csd->read_bl_len); + if (csd->read_bl_partial) + puts("Supports partial reads\n"); + else + puts("Does not support partial reads\n"); + printf("Write block length: %u\n", 1 << csd->write_bl_len); + if (csd->write_bl_partial) + puts("Supports partial writes\n"); + else + puts("Does not support partial writes\n"); + if (csd->wp_grp_enable) + printf("Supports group WP: %u\n", csd->wp_grp_size + 1); + else + puts("Does not support group WP\n"); + printf("Card capacity: %u bytes\n", + (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * + (1 << csd->read_bl_len)); + printf("File format: %u/%u\n", + csd->file_format_grp, csd->file_format); + puts("Write protection: "); + if (csd->perm_write_protect) + puts(" permanent"); + if (csd->tmp_write_protect) + puts(" temporary"); + putc('\n'); +} + +static int mmc_idle_cards(void) +{ + int ret; + + /* Reset and initialize all cards */ + ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); + if (ret) + return ret; + + /* Keep the bus idle for 74 clock cycles */ + return mmc_cmd(0, 0, NULL, INIT_CMD); +} + +static int sd_init_card(struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 1000; i++) { + ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, + resp, R3 | NID); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); + if (ret) + return ret; + sd_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Get RCA of the card that responded */ + ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + if (ret) + return ret; + + mmc_rca = resp[0] >> 16; + if (verbose) + printf("SD Card detected (RCA %u)\n", mmc_rca); + return 0; +} + +static int mmc_init_card(struct mmc_cid *cid, int verbose) +{ + unsigned long resp[4]; + int i, ret = 0; + + mmc_idle_cards(); + for (i = 0; i < 1000; i++) { + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp, + R3 | NID | OPEN_DRAIN); + if (ret || (resp[0] & 0x80000000)) + break; + ret = -ETIMEDOUT; + } + + if (ret) + return ret; + + /* Get CID of all cards. FIXME: Support more than one card */ + ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); + if (ret) + return ret; + mmc_parse_cid(cid, resp); + if (verbose) + mmc_dump_cid(cid); + + /* Set Relative Address of the card that responded */ + ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, + R1 | NCR | OPEN_DRAIN); + return ret; +} + +int mmc_init(int verbose) +{ + struct mmc_cid cid; + struct mmc_csd csd; + int ret; + + /* Initialize controller */ + mmci_writel(CR, MMCI_BIT(SWRST)); + mmci_writel(CR, MMCI_BIT(MCIEN)); + mmci_writel(DTOR, 0x5f); + mmci_writel(IDR, ~0UL); + mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + + ret = sd_init_card(&cid, verbose); + if (ret) { + mmc_rca = MMC_DEFAULT_RCA; + ret = mmc_init_card(&cid, verbose); + } + if (ret) + return ret; + + /* Get CSD from the card */ + ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR); + if (ret) + return ret; + if (verbose) + mmc_dump_csd(&csd); + + /* Initialize the blockdev structure */ + mmc_blkdev.if_type = IF_TYPE_MMC; + mmc_blkdev.part_type = PART_TYPE_DOS; + mmc_blkdev.block_read = mmc_bread; + sprintf((char *)mmc_blkdev.vendor, + "Man %02x%04x Snr %08x", + cid.mid, cid.oid, cid.psn); + strncpy((char *)mmc_blkdev.product, cid.pnm, + sizeof(mmc_blkdev.product)); + sprintf((char *)mmc_blkdev.revision, "%x %x", + cid.prv >> 4, cid.prv & 0x0f); + mmc_blkdev.blksz = 1 << csd.read_bl_len; + mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); + + mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); + +#if 0 + if (fat_register_device(&mmc_blkdev, 1)) + printf("Could not register MMC fat device\n"); +#else + init_part(&mmc_blkdev); +#endif + + return 0; +} + +int mmc_read(ulong src, uchar *dst, int size) +{ + return -ENOSYS; +} + +int mmc_write(uchar *src, ulong dst, int size) +{ + return -ENOSYS; +} + +int mmc2info(ulong addr) +{ + return 0; +} + +#endif /* CONFIG_MMC */ diff --git a/cpu/at32ap/atmel_mci.h b/cpu/at32ap/atmel_mci.h new file mode 100644 index 0000000000..0ffbc4fd09 --- /dev/null +++ b/cpu/at32ap/atmel_mci.h @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CPU_AT32AP_ATMEL_MCI_H__ +#define __CPU_AT32AP_ATMEL_MCI_H__ + +/* Atmel MultiMedia Card Interface (MCI) registers */ +#define MMCI_CR 0x0000 +#define MMCI_MR 0x0004 +#define MMCI_DTOR 0x0008 +#define MMCI_SDCR 0x000c +#define MMCI_ARGR 0x0010 +#define MMCI_CMDR 0x0014 +#define MMCI_RSPR 0x0020 +#define MMCI_RSPR1 0x0024 +#define MMCI_RSPR2 0x0028 +#define MMCI_RSPR3 0x002c +#define MMCI_RDR 0x0030 +#define MMCI_TDR 0x0034 +#define MMCI_SR 0x0040 +#define MMCI_IER 0x0044 +#define MMCI_IDR 0x0048 +#define MMCI_IMR 0x004c + +/* Bitfields in CR */ +#define MMCI_MCIEN_OFFSET 0 +#define MMCI_MCIEN_SIZE 1 +#define MMCI_MCIDIS_OFFSET 1 +#define MMCI_MCIDIS_SIZE 1 +#define MMCI_PWSEN_OFFSET 2 +#define MMCI_PWSEN_SIZE 1 +#define MMCI_PWSDIS_OFFSET 3 +#define MMCI_PWSDIS_SIZE 1 +#define MMCI_SWRST_OFFSET 7 +#define MMCI_SWRST_SIZE 1 + +/* Bitfields in MR */ +#define MMCI_CLKDIV_OFFSET 0 +#define MMCI_CLKDIV_SIZE 8 +#define MMCI_PWSDIV_OFFSET 8 +#define MMCI_PWSDIV_SIZE 3 +#define MMCI_PDCPADV_OFFSET 14 +#define MMCI_PDCPADV_SIZE 1 +#define MMCI_PDCMODE_OFFSET 15 +#define MMCI_PDCMODE_SIZE 1 +#define MMCI_BLKLEN_OFFSET 16 +#define MMCI_BLKLEN_SIZE 16 + +/* Bitfields in DTOR */ +#define MMCI_DTOCYC_OFFSET 0 +#define MMCI_DTOCYC_SIZE 4 +#define MMCI_DTOMUL_OFFSET 4 +#define MMCI_DTOMUL_SIZE 3 + +/* Bitfields in SDCR */ +#define MMCI_SCDSEL_OFFSET 0 +#define MMCI_SCDSEL_SIZE 4 +#define MMCI_SCDBUS_OFFSET 7 +#define MMCI_SCDBUS_SIZE 1 + +/* Bitfields in ARGR */ +#define MMCI_ARG_OFFSET 0 +#define MMCI_ARG_SIZE 32 + +/* Bitfields in CMDR */ +#define MMCI_CMDNB_OFFSET 0 +#define MMCI_CMDNB_SIZE 6 +#define MMCI_RSPTYP_OFFSET 6 +#define MMCI_RSPTYP_SIZE 2 +#define MMCI_SPCMD_OFFSET 8 +#define MMCI_SPCMD_SIZE 3 +#define MMCI_OPDCMD_OFFSET 11 +#define MMCI_OPDCMD_SIZE 1 +#define MMCI_MAXLAT_OFFSET 12 +#define MMCI_MAXLAT_SIZE 1 +#define MMCI_TRCMD_OFFSET 16 +#define MMCI_TRCMD_SIZE 2 +#define MMCI_TRDIR_OFFSET 18 +#define MMCI_TRDIR_SIZE 1 +#define MMCI_TRTYP_OFFSET 19 +#define MMCI_TRTYP_SIZE 2 + +/* Bitfields in RSPRx */ +#define MMCI_RSP_OFFSET 0 +#define MMCI_RSP_SIZE 32 + +/* Bitfields in SR/IER/IDR/IMR */ +#define MMCI_CMDRDY_OFFSET 0 +#define MMCI_CMDRDY_SIZE 1 +#define MMCI_RXRDY_OFFSET 1 +#define MMCI_RXRDY_SIZE 1 +#define MMCI_TXRDY_OFFSET 2 +#define MMCI_TXRDY_SIZE 1 +#define MMCI_BLKE_OFFSET 3 +#define MMCI_BLKE_SIZE 1 +#define MMCI_DTIP_OFFSET 4 +#define MMCI_DTIP_SIZE 1 +#define MMCI_NOTBUSY_OFFSET 5 +#define MMCI_NOTBUSY_SIZE 1 +#define MMCI_ENDRX_OFFSET 6 +#define MMCI_ENDRX_SIZE 1 +#define MMCI_ENDTX_OFFSET 7 +#define MMCI_ENDTX_SIZE 1 +#define MMCI_RXBUFF_OFFSET 14 +#define MMCI_RXBUFF_SIZE 1 +#define MMCI_TXBUFE_OFFSET 15 +#define MMCI_TXBUFE_SIZE 1 +#define MMCI_RINDE_OFFSET 16 +#define MMCI_RINDE_SIZE 1 +#define MMCI_RDIRE_OFFSET 17 +#define MMCI_RDIRE_SIZE 1 +#define MMCI_RCRCE_OFFSET 18 +#define MMCI_RCRCE_SIZE 1 +#define MMCI_RENDE_OFFSET 19 +#define MMCI_RENDE_SIZE 1 +#define MMCI_RTOE_OFFSET 20 +#define MMCI_RTOE_SIZE 1 +#define MMCI_DCRCE_OFFSET 21 +#define MMCI_DCRCE_SIZE 1 +#define MMCI_DTOE_OFFSET 22 +#define MMCI_DTOE_SIZE 1 +#define MMCI_OVRE_OFFSET 30 +#define MMCI_OVRE_SIZE 1 +#define MMCI_UNRE_OFFSET 31 +#define MMCI_UNRE_SIZE 1 + +/* Constants for DTOMUL */ +#define MMCI_DTOMUL_1_CYCLE 0 +#define MMCI_DTOMUL_16_CYCLES 1 +#define MMCI_DTOMUL_128_CYCLES 2 +#define MMCI_DTOMUL_256_CYCLES 3 +#define MMCI_DTOMUL_1024_CYCLES 4 +#define MMCI_DTOMUL_4096_CYCLES 5 +#define MMCI_DTOMUL_65536_CYCLES 6 +#define MMCI_DTOMUL_1048576_CYCLES 7 + +/* Constants for RSPTYP */ +#define MMCI_RSPTYP_NO_RESP 0 +#define MMCI_RSPTYP_48_BIT_RESP 1 +#define MMCI_RSPTYP_136_BIT_RESP 2 + +/* Constants for SPCMD */ +#define MMCI_SPCMD_NO_SPEC_CMD 0 +#define MMCI_SPCMD_INIT_CMD 1 +#define MMCI_SPCMD_SYNC_CMD 2 +#define MMCI_SPCMD_INT_CMD 4 +#define MMCI_SPCMD_INT_RESP 5 + +/* Constants for TRCMD */ +#define MMCI_TRCMD_NO_TRANS 0 +#define MMCI_TRCMD_START_TRANS 1 +#define MMCI_TRCMD_STOP_TRANS 2 + +/* Constants for TRTYP */ +#define MMCI_TRTYP_BLOCK 0 +#define MMCI_TRTYP_MULTI_BLOCK 1 +#define MMCI_TRTYP_STREAM 2 + +/* Bit manipulation macros */ +#define MMCI_BIT(name) \ + (1 << MMCI_##name##_OFFSET) +#define MMCI_BF(name,value) \ + (((value) & ((1 << MMCI_##name##_SIZE) - 1)) \ + << MMCI_##name##_OFFSET) +#define MMCI_BFEXT(name,value) \ + (((value) >> MMCI_##name##_OFFSET)\ + & ((1 << MMCI_##name##_SIZE) - 1)) +#define MMCI_BFINS(name,value,old) \ + (((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \ + << MMCI_##name##_OFFSET)) \ + | MMCI_BF(name,value)) + +/* Register access macros */ +#define mmci_readl(reg) \ + readl((void *)MMCI_BASE + MMCI_##reg) +#define mmci_writel(reg,value) \ + writel((value), (void *)MMCI_BASE + MMCI_##reg) + +#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */ diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 37e3ea040b..311466b781 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -26,33 +26,79 @@ #include <asm/sections.h> #include <asm/sysreg.h> +#include <asm/arch/clk.h> #include <asm/arch/memory-map.h> -#include <asm/arch/platform.h> #include "hsmc3.h" +#include "sm.h" + +/* Sanity checks */ +#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \ + || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \ + || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB) +# error Constraint fCPU >= fHSB >= fPB{A,B} violated +#endif +#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1)) +# error Invalid PLL multiplier and/or divider +#endif DECLARE_GLOBAL_DATA_PTR; +static void pm_init(void) +{ + uint32_t cksel; + +#ifdef CONFIG_PLL + /* Initialize the PLL */ + sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) + | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) + | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) + | SM_BF(PLLOPT, CFG_PLL0_OPT) + | SM_BF(PLLOSC, 0) + | SM_BIT(PLLEN))); + + /* Wait for lock */ + while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; +#endif + + /* Set up clocks for the CPU and all peripheral buses */ + cksel = 0; + if (CFG_CLKDIV_CPU) + cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); + if (CFG_CLKDIV_HSB) + cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); + if (CFG_CLKDIV_PBA) + cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); + if (CFG_CLKDIV_PBB) + cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); + sm_writel(PM_CKSEL, cksel); + + gd->cpu_hz = get_cpu_clk_rate(); + +#ifdef CONFIG_PLL + /* Use PLL0 as main clock */ + sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); +#endif +} + int cpu_init(void) { - const struct device *hebi; extern void _evba(void); char *p; gd->cpu_hz = CFG_OSC0_HZ; - /* fff03400: 00010001 04030402 00050005 10011103 */ - hebi = get_device(DEVICE_HEBI); - hsmc3_writel(hebi, MODE0, 0x00031103); - hsmc3_writel(hebi, CYCLE0, 0x000c000d); - hsmc3_writel(hebi, PULSE0, 0x0b0a0906); - hsmc3_writel(hebi, SETUP0, 0x00010002); + /* TODO: Move somewhere else, but needs to be run before we + * increase the clock frequency. */ + hsmc3_writel(MODE0, 0x00031103); + hsmc3_writel(CYCLE0, 0x000c000d); + hsmc3_writel(PULSE0, 0x0b0a0906); + hsmc3_writel(SETUP0, 0x00010002); pm_init(); sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - gd->console_uart = get_device(CFG_CONSOLE_UART_DEV); /* Lock everything that mess with the flash in the icache */ for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ); diff --git a/cpu/at32ap/device.c b/cpu/at32ap/device.c deleted file mode 100644 index 89914b6b56..0000000000 --- a/cpu/at32ap/device.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> - -#include <asm/arch/platform.h> - -#include "sm.h" - -struct device_state { - int refcount; -}; - -static struct device_state device_state[NR_DEVICES]; - -static int claim_resource(const struct resource *res) -{ - int ret = 0; - - switch (res->type) { - case RESOURCE_GPIO: - ret = gpio_set_func(res->u.gpio.gpio_dev, - res->u.gpio.start, - res->u.gpio.nr_pins, - res->u.gpio.func); - break; - case RESOURCE_CLOCK: - ret = pm_enable_clock(res->u.clock.id, res->u.clock.index); - break; - } - - return ret; -} - -static void free_resource(const struct resource *res) -{ - switch (res->type) { - case RESOURCE_GPIO: - gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start, - res->u.gpio.nr_pins); - break; - case RESOURCE_CLOCK: - pm_disable_clock(res->u.clock.id, res->u.clock.index); - break; - } -} - -static int init_dev(const struct device *dev) -{ - unsigned int i; - int ret = 0; - - for (i = 0; i < dev->nr_resources; i++) { - ret = claim_resource(&dev->resource[i]); - if (ret) - goto cleanup; - } - - return 0; - -cleanup: - while (i--) - free_resource(&dev->resource[i]); - - return ret; -} - -const struct device *get_device(enum device_id devid) -{ - struct device_state *devstate; - const struct device *dev; - unsigned long flags; - int initialized = 0; - int ret = 0; - - devstate = &device_state[devid]; - dev = &chip_device[devid]; - - flags = disable_interrupts(); - if (devstate->refcount++) - initialized = 1; - if (flags) - enable_interrupts(); - - if (!initialized) - ret = init_dev(dev); - - return ret ? NULL : dev; -} - -void put_device(const struct device *dev) -{ - struct device_state *devstate; - unsigned long devid, flags; - - devid = (unsigned long)(dev - chip_device) / sizeof(struct device); - devstate = &device_state[devid]; - - flags = disable_interrupts(); - devstate--; - if (!devstate) { - unsigned int i; - for (i = 0; i < dev->nr_resources; i++) - free_resource(&dev->resource[i]); - } - if (flags) - enable_interrupts(); -} diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S index b52d798be3..a6fc68867a 100644 --- a/cpu/at32ap/entry.S +++ b/cpu/at32ap/entry.S @@ -42,8 +42,7 @@ timer_interrupt_handler: * We're running at interrupt level 3, so we don't need to save * r8-r12 or lr to the stack. */ - mov r8, lo(timer_overflow) - orh r8, hi(timer_overflow) + lda.w r8, timer_overflow ld.w r9, r8[0] mov r10, -1 mtsr SYSREG_COMPARE, r10 diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c index 4123c44616..0672685cd0 100644 --- a/cpu/at32ap/exception.c +++ b/cpu/at32ap/exception.c @@ -24,6 +24,8 @@ #include <asm/sysreg.h> #include <asm/ptrace.h> +DECLARE_GLOBAL_DATA_PTR; + static const char * const cpu_modes[8] = { "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1", "Interrupt level 2", "Interrupt level 3", "Exception", "NMI" @@ -109,11 +111,10 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) printf("CPU Mode: %s\n", cpu_modes[mode]); /* Avoid exception loops */ - if (regs->sp >= CFG_INIT_SP_ADDR - || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE)) + if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end) printf("\nStack pointer seems bogus, won't do stack dump\n"); else - dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR); + dump_mem("\nStack: ", regs->sp, gd->stack_end); panic("Unhandled exception\n"); } diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index f36da35452..a936e03166 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -25,17 +25,11 @@ #include <asm/io.h> #include <asm/sdram.h> -#include <asm/arch/platform.h> +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> #include "hsdramc1.h" -struct hsdramc { - const struct device *hebi; - void *regs; -}; - -static struct hsdramc hsdramc; - unsigned long sdram_init(const struct sdram_info *info) { unsigned long *sdram = (unsigned long *)uncached(info->phys_addr); @@ -44,16 +38,6 @@ unsigned long sdram_init(const struct sdram_info *info) unsigned long bus_hz; unsigned int i; - hsdramc.hebi = get_device(DEVICE_HEBI); - if (!hsdramc.hebi) - return 0; - - /* FIXME: Both of these lines are complete hacks */ - hsdramc.regs = hsdramc.hebi->regs + 0x400; - bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id); - - cpu_enable_sdram(); - tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) | HSDRAMC1_BF(NR, info->row_bits - 11) | HSDRAMC1_BF(NB, info->bank_bits - 1) @@ -74,7 +58,7 @@ unsigned long sdram_init(const struct sdram_info *info) + info->bank_bits + 2); #endif - hsdramc1_writel(&hsdramc, CR, tmp); + hsdramc1_writel(CR, tmp); /* * Initialization sequence for SDRAM, from the data sheet: @@ -87,15 +71,15 @@ unsigned long sdram_init(const struct sdram_info *info) /* * 2. A Precharge All command is issued to the SDRAM */ - hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE); - hsdramc1_readl(&hsdramc, MR); + hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE); + hsdramc1_readl(MR); writel(0, sdram); /* * 3. Eight auto-refresh (CBR) cycles are provided */ - hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH); - hsdramc1_readl(&hsdramc, MR); + hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH); + hsdramc1_readl(MR); for (i = 0; i < 8; i++) writel(0, sdram); @@ -106,8 +90,8 @@ unsigned long sdram_init(const struct sdram_info *info) * * CAS from info struct, burst length 1, serial burst type */ - hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE); - hsdramc1_readl(&hsdramc, MR); + hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE); + hsdramc1_readl(MR); writel(0, sdram + (info->cas << 4)); /* @@ -117,9 +101,9 @@ unsigned long sdram_init(const struct sdram_info *info) * From the timing diagram, it looks like tMRD is 3 * cycles...try a dummy read from the peripheral bus. */ - hsdramc1_readl(&hsdramc, MR); - hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL); - hsdramc1_readl(&hsdramc, MR); + hsdramc1_readl(MR); + hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL); + hsdramc1_readl(MR); writel(0, sdram); /* @@ -128,7 +112,8 @@ unsigned long sdram_init(const struct sdram_info *info) * * 15.6 us is a typical value for a burst of length one */ - hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000); + bus_hz = get_sdram_clk_rate(); + hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000); printf("SDRAM: %u MB at address 0x%08lx\n", sdram_size >> 20, info->phys_addr); diff --git a/cpu/at32ap/hsdramc1.h b/cpu/at32ap/hsdramc1.h index ce229bca1f..305d2cb5d3 100644 --- a/cpu/at32ap/hsdramc1.h +++ b/cpu/at32ap/hsdramc1.h @@ -135,9 +135,9 @@ | HSDRAMC1_BF(name,value)) /* Register access macros */ -#define hsdramc1_readl(port,reg) \ - readl((port)->regs + HSDRAMC1_##reg) -#define hsdramc1_writel(port,reg,value) \ - writel((value), (port)->regs + HSDRAMC1_##reg) +#define hsdramc1_readl(reg) \ + readl((void *)HSDRAMC_BASE + HSDRAMC1_##reg) +#define hsdramc1_writel(reg,value) \ + writel((value), (void *)HSDRAMC_BASE + HSDRAMC1_##reg) #endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff --git a/cpu/at32ap/hsmc3.h b/cpu/at32ap/hsmc3.h index ec78cee714..ca533b922e 100644 --- a/cpu/at32ap/hsmc3.h +++ b/cpu/at32ap/hsmc3.h @@ -118,9 +118,9 @@ | HSMC3_BF(name,value)) /* Register access macros */ -#define hsmc3_readl(port,reg) \ - readl((port)->regs + HSMC3_##reg) -#define hsmc3_writel(port,reg,value) \ - writel((value), (port)->regs + HSMC3_##reg) +#define hsmc3_readl(reg) \ + readl((void *)HSMC_BASE + HSMC3_##reg) +#define hsmc3_writel(reg,value) \ + writel((value), (void *)HSMC_BASE + HSMC3_##reg) #endif /* __CPU_AT32AP_HSMC3_H__ */ diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c index d720cfa942..c9e04993c7 100644 --- a/cpu/at32ap/interrupts.c +++ b/cpu/at32ap/interrupts.c @@ -27,7 +27,7 @@ #include <asm/processor.h> #include <asm/sysreg.h> -#include <asm/arch/platform.h> +#include <asm/arch/memory-map.h> #define HANDLER_MASK 0x00ffffff #define INTLEV_SHIFT 30 @@ -44,8 +44,6 @@ volatile unsigned long timer_overflow; */ static unsigned long tb_factor; -static const struct device *intc_dev; - unsigned long get_tbclk(void) { return gd->cpu_hz; @@ -117,16 +115,19 @@ void udelay(unsigned long usec) static int set_interrupt_handler(unsigned int nr, void (*handler)(void), unsigned int priority) { + extern void _evba(void); unsigned long intpr; unsigned long handler_addr = (unsigned long)handler; + handler_addr -= (unsigned long)&_evba; + if ((handler_addr & HANDLER_MASK) != handler_addr || (priority & INTLEV_MASK) != priority) return -EINVAL; intpr = (handler_addr & HANDLER_MASK); intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT; - writel(intpr, intc_dev->regs + 4 * nr); + writel(intpr, (void *)INTC_BASE + 4 * nr); return 0; } @@ -143,10 +144,7 @@ void timer_init(void) do_div(tmp, gd->cpu_hz); tb_factor = (u32)tmp; - intc_dev = get_device(DEVICE_INTC); - - if (!intc_dev - || set_interrupt_handler(0, &timer_interrupt_handler, 3)) + if (set_interrupt_handler(0, &timer_interrupt_handler, 3)) return; /* For all practical purposes, this gives us an overflow interrupt */ diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c index 8b6c3a35df..9ba0b8ea8b 100644 --- a/cpu/at32ap/pio.c +++ b/cpu/at32ap/pio.c @@ -21,74 +21,40 @@ */ #include <common.h> -#include <asm/errno.h> #include <asm/io.h> -#include <asm/arch/platform.h> +#include <asm/arch/gpio.h> +#include <asm/arch/memory-map.h> #include "pio2.h" -struct pio_state { - const struct device *dev; - u32 alloc_mask; -}; - -static struct pio_state pio_state[CFG_NR_PIOS]; - -int gpio_set_func(enum device_id gpio_devid, unsigned int start, - unsigned int nr_pins, enum gpio_func func) +void gpio_select_periph_A(unsigned int pin, int use_pullup) { - const struct device *gpio; - struct pio_state *state; - u32 mask; - - state = &pio_state[gpio_devid - DEVICE_PIOA]; - - gpio = get_device(gpio_devid); - if (!gpio) - return -EBUSY; - - state->dev = gpio; - mask = ((1 << nr_pins) - 1) << start; - - if (mask & state->alloc_mask) { - put_device(gpio); - return -EBUSY; - } - state->alloc_mask |= mask; - - switch (func) { - case GPIO_FUNC_GPIO: - /* TODO */ - return -EINVAL; - case GPIO_FUNC_A: - pio2_writel(gpio, ASR, mask); - pio2_writel(gpio, PDR, mask); - pio2_writel(gpio, PUDR, mask); - break; - case GPIO_FUNC_B: - pio2_writel(gpio, BSR, mask); - pio2_writel(gpio, PDR, mask); - pio2_writel(gpio, PUDR, mask); - break; - } - - return 0; + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + pio2_writel(base, ASR, mask); + pio2_writel(base, PDR, mask); + if (use_pullup) + pio2_writel(base, PUER, mask); + else + pio2_writel(base, PUDR, mask); } -void gpio_free(enum device_id gpio_devid, unsigned int start, - unsigned int nr_pins) +void gpio_select_periph_B(unsigned int pin, int use_pullup) { - const struct device *gpio; - struct pio_state *state; - u32 mask; - - state = &pio_state[gpio_devid - DEVICE_PIOA]; - gpio = state->dev; - mask = ((1 << nr_pins) - 1) << start; - - pio2_writel(gpio, ODR, mask); - pio2_writel(gpio, PER, mask); - - state->alloc_mask &= ~mask; - put_device(gpio); + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + pio2_writel(base, BSR, mask); + pio2_writel(base, PDR, mask); + if (use_pullup) + pio2_writel(base, PUER, mask); + else + pio2_writel(base, PUDR, mask); } diff --git a/cpu/at32ap/pio2.h b/cpu/at32ap/pio2.h index 6b79de3c72..9719ea8c43 100644 --- a/cpu/at32ap/pio2.h +++ b/cpu/at32ap/pio2.h @@ -36,9 +36,9 @@ #define PIO2_OWSR 0x00a8 /* Register access macros */ -#define pio2_readl(port,reg) \ - readl((port)->regs + PIO2_##reg) -#define pio2_writel(port,reg,value) \ - writel((value), (port)->regs + PIO2_##reg) +#define pio2_readl(base,reg) \ + readl((void *)base + PIO2_##reg) +#define pio2_writel(base,reg,value) \ + writel((value), (void *)base + PIO2_##reg) #endif /* __CPU_AT32AP_PIO2_H__ */ diff --git a/cpu/at32ap/pm.c b/cpu/at32ap/pm.c index 01ac325ee8..c78d547f85 100644 --- a/cpu/at32ap/pm.c +++ b/cpu/at32ap/pm.c @@ -26,138 +26,17 @@ #include <asm/io.h> #include <asm/arch/memory-map.h> -#include <asm/arch/platform.h> #include "sm.h" -/* Sanity checks */ -#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \ - || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \ - || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB) -# error Constraint fCPU >= fHSB >= fPB{A,B} violated -#endif -#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1)) -# error Invalid PLL multiplier and/or divider -#endif - -DECLARE_GLOBAL_DATA_PTR; - -struct clock_domain_state { - const struct device *bridge; - unsigned long freq; - u32 mask; -}; -static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS]; - -int pm_enable_clock(enum clock_domain_id id, unsigned int index) -{ - const struct clock_domain *ckd = &chip_clock[id]; - struct clock_domain_state *state = &ckd_state[id]; - - if (ckd->bridge != NO_DEVICE) { - state->bridge = get_device(ckd->bridge); - if (!state->bridge) - return -EBUSY; - } - - state->mask |= 1 << index; - if (gd->sm) - writel(state->mask, gd->sm->regs + ckd->reg); - - return 0; -} - -void pm_disable_clock(enum clock_domain_id id, unsigned int index) -{ - const struct clock_domain *ckd = &chip_clock[id]; - struct clock_domain_state *state = &ckd_state[id]; - - state->mask &= ~(1 << index); - if (gd->sm) - writel(state->mask, gd->sm->regs + ckd->reg); - - if (ckd->bridge) - put_device(state->bridge); -} - -unsigned long pm_get_clock_freq(enum clock_domain_id domain) -{ - return ckd_state[domain].freq; -} - -void pm_init(void) -{ - uint32_t cksel = 0; - unsigned long main_clock; - - /* Make sure we don't disable any device we're already using */ - get_device(DEVICE_HRAMC); - get_device(DEVICE_HEBI); - - /* Enable the PICO as well */ - ckd_state[CLOCK_CPU].mask |= 1; - - gd->sm = get_device(DEVICE_SM); - if (!gd->sm) - panic("Unable to claim system manager device!\n"); - - /* Disable any devices that haven't been explicitly claimed */ - sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask); - sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask); - sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask); - sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask); #ifdef CONFIG_PLL - /* Initialize the PLL */ - main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL; - - sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) - | SM_BF(PLLMUL, CFG_PLL0_MUL - 1) - | SM_BF(PLLDIV, CFG_PLL0_DIV - 1) - | SM_BF(PLLOPT, CFG_PLL0_OPT) - | SM_BF(PLLOSC, 0) - | SM_BIT(PLLEN))); - - /* Wait for lock */ - while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ; +#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) #else - main_clock = CFG_OSC0_HZ; +#define MAIN_CLK_RATE (CFG_OSC0_HZ) #endif - /* Set up clocks for the CPU and all peripheral buses */ - if (CFG_CLKDIV_CPU) { - cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); - ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU); - } else { - ckd_state[CLOCK_CPU].freq = main_clock; - } - if (CFG_CLKDIV_HSB) { - cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); - ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB); - } else { - ckd_state[CLOCK_HSB].freq = main_clock; - } - if (CFG_CLKDIV_PBA) { - cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); - ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA); - } else { - ckd_state[CLOCK_PBA].freq = main_clock; - } - if (CFG_CLKDIV_PBB) { - cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); - ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB); - } else { - ckd_state[CLOCK_PBB].freq = main_clock; - } - sm_writel(gd->sm, PM_CKSEL, cksel); - - /* CFG_HZ currently depends on cpu_hz */ - gd->cpu_hz = ckd_state[CLOCK_CPU].freq; +DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PLL - /* Use PLL0 as main clock */ - sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL)); -#endif -} #endif /* CFG_POWER_MANAGER */ diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/sm.h index ce81ef0a46..6492c8e81d 100644 --- a/cpu/at32ap/sm.h +++ b/cpu/at32ap/sm.h @@ -196,9 +196,9 @@ | SM_BF(name,value)) /* Register access macros */ -#define sm_readl(port,reg) \ - readl((port)->regs + SM_##reg) -#define sm_writel(port,reg,value) \ - writel((value), (port)->regs + SM_##reg) +#define sm_readl(reg) \ + readl((void *)SM_BASE + SM_##reg) +#define sm_writel(reg,value) \ + writel((value), (void *)SM_BASE + SM_##reg) #endif /* __CPU_AT32AP_SM_H__ */ diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S index 79ee33b1fa..ab8c2b73d8 100644 --- a/cpu/at32ap/start.S +++ b/cpu/at32ap/start.S @@ -70,32 +70,12 @@ _start: 2: lddpc sp, sp_init - /* - * Relocate the data section and initialize .bss. Everything - * is guaranteed to be at least doubleword aligned by the - * linker script. - */ - lddpc r12, .Ldata_vma - lddpc r11, .Ldata_lma - lddpc r10, .Ldata_end - sub r10, r12 -4: ld.d r8, r11++ - sub r10, 8 - st.d r12++, r8 - brne 4b - - mov r8, 0 - mov r9, 0 - lddpc r10, .Lbss_end - sub r10, r12 -4: sub r10, 8 - st.d r12++, r8 - brne 4b - /* Initialize the GOT pointer */ lddpc r6, got_init 3: rsub r6, pc - ld.w pc, r6[start_u_boot@got] + + /* Let's go */ + rjmp board_init_f .align 2 .type sp_init,@object @@ -103,11 +83,82 @@ sp_init: .long CFG_INIT_SP_ADDR got_init: .long 3b - _GLOBAL_OFFSET_TABLE_ -.Ldata_lma: - .long __data_lma -.Ldata_vma: - .long _data -.Ldata_end: - .long _edata -.Lbss_end: - .long _end + + /* + * void relocate_code(new_sp, new_gd, monitor_addr) + * + * Relocate the u-boot image into RAM and continue from there. + * Does not return. + */ + .global relocate_code + .type relocate_code,@function +relocate_code: + mov sp, r12 /* use new stack */ + mov r12, r11 /* save new_gd */ + mov r11, r10 /* save destination address */ + + /* copy .text section and flush the cache along the way */ + lda.w r8, _text + lda.w r9, _etext + sub lr, r10, r8 /* relocation offset */ + +1: ldm r8++, r0-r3 + stm r10, r0-r3 + sub r10, -16 + ldm r8++, r0-r3 + stm r10, r0-r3 + sub r10, -16 + cp.w r8, r9 + cache r10[-4], 0x0d /* dcache clean/invalidate */ + cache r10[-4], 0x01 /* icache invalidate */ + brlt 1b + + /* flush write buffer */ + sync 0 + + /* copy data sections */ + lda.w r9, _edata +1: ld.d r0, r8++ + st.d r10++, r0 + cp.w r8, r9 + brlt 1b + + /* zero out .bss */ + mov r0, 0 + mov r1, 0 + lda.w r9, _end + sub r9, r8 +1: st.d r10++, r0 + sub r9, 8 + brgt 1b + + /* jump to RAM */ + sub r0, pc, . - in_ram + add pc, r0, lr + + .align 2 +in_ram: + /* find the new GOT and relocate it */ + lddpc r6, got_init_reloc +3: rsub r6, pc + mov r8, r6 + lda.w r9, _egot + lda.w r10, _got + sub r9, r10 +1: ld.w r0, r8[0] + add r0, lr + st.w r8++, r0 + sub r9, 4 + brgt 1b + + /* Move the exception handlers */ + mfsr r2, SYSREG_EVBA + add r2, lr + mtsr SYSREG_EVBA, r2 + + /* Do the rest of the initialization sequence */ + call board_init_r + + .align 2 +got_init_reloc: + .long 3b - _GLOBAL_OFFSET_TABLE_ diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile index 90018f3f52..dd4f299acd 100644 --- a/cpu/bf533/Makefile +++ b/cpu/bf533/Makefile @@ -1,6 +1,6 @@ # U-boot - Makefile # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,8 +20,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # include $(TOPDIR)/config.mk diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h index 0a04f3e8ce..25b96a9f69 100644 --- a/cpu/bf533/bf533_serial.h +++ b/cpu/bf533/bf533_serial.h @@ -1,7 +1,7 @@ /* * U-boot - bf533_serial.h Serial Driver defines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. @@ -38,8 +38,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _Bf533_SERIAL_H diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk index 10817d9ea9..6a713c3f51 100644 --- a/cpu/bf533/config.mk +++ b/cpu/bf533/config.mk @@ -1,6 +1,6 @@ # U-boot - config.mk # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,8 +20,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5 diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c index ac8ec517ff..8118861f8d 100644 --- a/cpu/bf533/cpu.c +++ b/cpu/bf533/cpu.c @@ -1,7 +1,7 @@ /* * U-boot - cpu.c CPU specific functions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> @@ -93,7 +93,7 @@ void icache_enable(void) /* Fill the rest with invalid entry */ if (j <= 15) { - for (; j <= 16; j++) { + for (; j < 16; j++) { debug("filling %i with 0", j); *I1++ = 0x0; } @@ -169,7 +169,7 @@ void dcache_enable(void) /* Fill the rest with invalid entry */ if (j <= 15) { - for (; j <= 16; j++) { + for (; j < 16; j++) { debug("filling %i with 0", j); *I1++ = 0x0; } diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h index 821363e764..b6b73b1d8f 100644 --- a/cpu/bf533/cpu.h +++ b/cpu/bf533/cpu.h @@ -1,7 +1,7 @@ /* * U-boot - cpu.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _CPU_H_ diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S index 0512f3bf92..62e3d65ae7 100644 --- a/cpu/bf533/flush.S +++ b/cpu/bf533/flush.S @@ -1,9 +1,9 @@ -/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. - * Copyright (C) 2004 LG SOft India. All Rights Reserved. +/* Copyright (C) 2003-2007 Analog Devices Inc. * * This file is subject to the terms and conditions of the GNU General Public * License. */ + #define ASSEMBLY #include <asm/linkage.h> diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S index 524da8f511..c356d53aa6 100644 --- a/cpu/bf533/interrupt.S +++ b/cpu/bf533/interrupt.S @@ -1,7 +1,7 @@ /* * U-boot - interrupt.S Processing of interrupts and exception handling * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -35,8 +35,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define ASSEMBLY diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c index 9317f26d98..14d06cf8df 100644 --- a/cpu/bf533/interrupts.c +++ b/cpu/bf533/interrupts.c @@ -1,7 +1,7 @@ /* * U-boot - interrupts.c Interrupt related routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on interrupts.c * Copyright 1996 Roman Zippel @@ -30,8 +30,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c index f476f14342..55866896a0 100644 --- a/cpu/bf533/ints.c +++ b/cpu/bf533/ints.c @@ -1,7 +1,7 @@ /* * U-boot - ints.c Interrupt related routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on ints.c * @@ -32,8 +32,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 11a46be964..6cab5daac7 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -1,7 +1,7 @@ /* * U-boot - serial.c Serial driver for BF533 * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART. @@ -38,8 +38,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 94556d681f..67a60cf21e 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -1,7 +1,7 @@ /* * U-boot - start.S Startup file of u-boot for BF533/BF561 * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on head.S * Copyright (c) 2003 Metrowerks/Motorola @@ -26,8 +26,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S index 72cfafb5e9..6d4731b696 100644 --- a/cpu/bf533/start1.S +++ b/cpu/bf533/start1.S @@ -1,7 +1,7 @@ /* * U-boot - start1.S Code running out of RAM after relocation * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define ASSEMBLY diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c index 248e34f3f5..19b1fde41d 100644 --- a/cpu/bf533/traps.c +++ b/cpu/bf533/traps.c @@ -1,7 +1,7 @@ /* * U-boot - traps.c Routines related to interrupts and exceptions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * No original Copyright holder listed, @@ -29,8 +29,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> @@ -39,7 +39,6 @@ #include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/page.h> #include <asm/machdep.h> #include "cpu.h" #include <asm/arch/anomaly.h> diff --git a/cpu/bf537/Makefile b/cpu/bf537/Makefile index 61c733886b..8b0f9c0e93 100644 --- a/cpu/bf537/Makefile +++ b/cpu/bf537/Makefile @@ -1,6 +1,6 @@ # U-boot - Makefile # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,8 +20,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # include $(TOPDIR)/config.mk diff --git a/cpu/bf537/config.mk b/cpu/bf537/config.mk index 4d57d9c9ad..8a35789f13 100644 --- a/cpu/bf537/config.mk +++ b/cpu/bf537/config.mk @@ -1,6 +1,6 @@ # U-boot - config.mk # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,8 +20,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5 diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c index cb8dc3cd16..62f603bdb0 100644 --- a/cpu/bf537/cpu.c +++ b/cpu/bf537/cpu.c @@ -1,7 +1,7 @@ /* * U-boot - cpu.c CPU specific functions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf537/cpu.h b/cpu/bf537/cpu.h index 821363e764..b6b73b1d8f 100644 --- a/cpu/bf537/cpu.h +++ b/cpu/bf537/cpu.h @@ -1,7 +1,7 @@ /* * U-boot - cpu.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _CPU_H_ diff --git a/cpu/bf537/flush.S b/cpu/bf537/flush.S index c260a8f963..fbd26cc92b 100644 --- a/cpu/bf537/flush.S +++ b/cpu/bf537/flush.S @@ -1,9 +1,9 @@ -/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. - * Copyright (C) 2004 LG SOft India. All Rights Reserved. +/* Copyright (C) 2003-2007 Analog Devices Inc. * * This file is subject to the terms and conditions of the GNU General Public * License. */ + #define ASSEMBLY #include <asm/linkage.h> diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S index a8be34f027..a71df55a93 100644 --- a/cpu/bf537/interrupt.S +++ b/cpu/bf537/interrupt.S @@ -1,7 +1,7 @@ /* * U-boot - interrupt.S Processing of interrupts and exception handling * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -35,8 +35,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define ASSEMBLY diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c index 2ca76ecb3c..d2213b1156 100644 --- a/cpu/bf537/interrupts.c +++ b/cpu/bf537/interrupts.c @@ -1,7 +1,7 @@ /* * U-boot - interrupts.c Interrupt related routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on interrupts.c * Copyright 1996 Roman Zippel @@ -30,8 +30,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c index f476f14342..55866896a0 100644 --- a/cpu/bf537/ints.c +++ b/cpu/bf537/ints.c @@ -1,7 +1,7 @@ /* * U-boot - ints.c Interrupt related routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on ints.c * @@ -32,8 +32,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index dd4f916d50..e04d08a0e7 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -1,7 +1,7 @@ /* * U-boot - serial.c Serial driver for BF537 * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * bf537_serial.c: Serial driver for BlackFin BF537 internal UART. @@ -38,8 +38,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h index c9ee3dc068..76555c279d 100644 --- a/cpu/bf537/serial.h +++ b/cpu/bf537/serial.h @@ -1,7 +1,7 @@ /* * U-boot - bf537_serial.h Serial Driver defines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. @@ -38,8 +38,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _Bf537_SERIAL_H diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S index 264e9b6080..4e02bcb9e5 100644 --- a/cpu/bf537/start.S +++ b/cpu/bf537/start.S @@ -1,7 +1,7 @@ /* * U-boot - start.S Startup file of u-boot for BF537 * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on head.S * Copyright (c) 2003 Metrowerks/Motorola @@ -26,8 +26,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/cpu/bf537/start1.S b/cpu/bf537/start1.S index 72cfafb5e9..6d4731b696 100644 --- a/cpu/bf537/start1.S +++ b/cpu/bf537/start1.S @@ -1,7 +1,7 @@ /* * U-boot - start1.S Code running out of RAM after relocation * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define ASSEMBLY diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c index 994ece8f64..4e18e27df4 100644 --- a/cpu/bf537/traps.c +++ b/cpu/bf537/traps.c @@ -1,7 +1,7 @@ /* * U-boot - traps.c Routines related to interrupts and exceptions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * No original Copyright holder listed, @@ -29,8 +29,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> @@ -39,7 +39,6 @@ #include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/page.h> #include <asm/machdep.h> #include "cpu.h" #include <asm/arch/anomaly.h> diff --git a/cpu/bf561/Makefile b/cpu/bf561/Makefile index ee7842a5d3..29471694d9 100644 --- a/cpu/bf561/Makefile +++ b/cpu/bf561/Makefile @@ -1,6 +1,6 @@ # U-boot - Makefile # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,8 +20,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # include $(TOPDIR)/config.mk diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk index c49a0ba5fe..f4dc04bfc9 100644 --- a/cpu/bf561/config.mk +++ b/cpu/bf561/config.mk @@ -1,6 +1,6 @@ # U-boot - config.mk # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,8 +20,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5 diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c index a7b53d8a2d..5b907cd1ef 100644 --- a/cpu/bf561/cpu.c +++ b/cpu/bf561/cpu.c @@ -1,7 +1,7 @@ /* * U-boot - cpu.c CPU specific functions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf561/cpu.h b/cpu/bf561/cpu.h index 821363e764..b6b73b1d8f 100644 --- a/cpu/bf561/cpu.h +++ b/cpu/bf561/cpu.h @@ -1,7 +1,7 @@ /* * U-boot - cpu.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _CPU_H_ diff --git a/cpu/bf561/flush.S b/cpu/bf561/flush.S index 7e12c8305c..0140a60c49 100644 --- a/cpu/bf561/flush.S +++ b/cpu/bf561/flush.S @@ -1,9 +1,9 @@ -/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. - * Copyright (C) 2004 LG SOft India. All Rights Reserved. +/* Copyright (C) 2003-2007 Analog Devices Inc. * * This file is subject to the terms and conditions of the GNU General Public * License. */ + #define ASSEMBLY #include <asm/linkage.h> diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S index f82fd9b824..21839ce7de 100644 --- a/cpu/bf561/interrupt.S +++ b/cpu/bf561/interrupt.S @@ -1,7 +1,7 @@ /* * U-boot - interrupt.S Processing of interrupts and exception handling * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -35,8 +35,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define ASSEMBLY diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c index e314f60d2d..ecbc6addfc 100644 --- a/cpu/bf561/interrupts.c +++ b/cpu/bf561/interrupts.c @@ -1,7 +1,7 @@ /* * U-boot - interrupts.c Interrupt related routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on interrupts.c * Copyright 1996 Roman Zippel @@ -30,8 +30,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c index 328e5d8ef6..27a38a3493 100644 --- a/cpu/bf561/ints.c +++ b/cpu/bf561/ints.c @@ -1,7 +1,7 @@ /* * U-boot - ints.c Interrupt related routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on ints.c * @@ -32,8 +32,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index baec1d3e4d..7f5c695361 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -1,7 +1,7 @@ /* * U-boot - serial.c Serial driver for BF561 * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART. @@ -38,8 +38,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h index 98c1242a32..c1cbf36acf 100644 --- a/cpu/bf561/serial.h +++ b/cpu/bf561/serial.h @@ -1,7 +1,7 @@ /* * U-boot - bf561_serial.h Serial Driver defines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. @@ -38,8 +38,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _Bf561_SERIAL_H diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S index 9333648048..bd26cf32f6 100644 --- a/cpu/bf561/start.S +++ b/cpu/bf561/start.S @@ -1,7 +1,7 @@ /* * U-boot - start.S Startup file of u-boot for BF533/BF561 * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on head.S * Copyright (c) 2003 Metrowerks/Motorola @@ -26,8 +26,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/cpu/bf561/start1.S b/cpu/bf561/start1.S index 72cfafb5e9..6d4731b696 100644 --- a/cpu/bf561/start1.S +++ b/cpu/bf561/start1.S @@ -1,7 +1,7 @@ /* * U-boot - start1.S Code running out of RAM after relocation * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define ASSEMBLY diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c index f5ff3a8079..7e2dcd17ad 100644 --- a/cpu/bf561/traps.c +++ b/cpu/bf561/traps.c @@ -1,7 +1,7 @@ /* * U-boot - traps.c Routines related to interrupts and exceptions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * No original Copyright holder listed, @@ -29,8 +29,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 21b16463cd..e934ba638f 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -300,92 +300,174 @@ void watchdog_reset (void) #if defined(CONFIG_OF_LIBFDT) /* + * "Setter" functions used to add/modify FDT entries. + */ +static int fdt_set_eth0(void *fdt, int nodeoffset, const char *name, bd_t *bd) +{ + /* + * Fix it up if it exists, don't create it if it doesn't exist. + */ + if (fdt_get_property(fdt, nodeoffset, name, 0)) { + return fdt_setprop(fdt, nodeoffset, name, bd->bi_enetaddr, 6); + } + return -FDT_ERR_NOTFOUND; +} +#ifdef CONFIG_HAS_ETH1 +/* second onboard ethernet port */ +static int fdt_set_eth1(void *fdt, int nodeoffset, const char *name, bd_t *bd) +{ + /* + * Fix it up if it exists, don't create it if it doesn't exist. + */ + if (fdt_get_property(fdt, nodeoffset, name, 0)) { + return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet1addr, 6); + } + return -FDT_ERR_NOTFOUND; +} +#endif +#ifdef CONFIG_HAS_ETH2 +/* third onboard ethernet port */ +static int fdt_set_eth2(void *fdt, int nodeoffset, const char *name, bd_t *bd) +{ + /* + * Fix it up if it exists, don't create it if it doesn't exist. + */ + if (fdt_get_property(fdt, nodeoffset, name, 0)) { + return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet2addr, 6); + } + return -FDT_ERR_NOTFOUND; +} +#endif +#ifdef CONFIG_HAS_ETH3 +/* fourth onboard ethernet port */ +static int fdt_set_eth3(void *fdt, int nodeoffset, const char *name, bd_t *bd) +{ + /* + * Fix it up if it exists, don't create it if it doesn't exist. + */ + if (fdt_get_property(fdt, nodeoffset, name, 0)) { + return fdt_setprop(fdt, nodeoffset, name, bd->bi_enet3addr, 6); + } + return -FDT_ERR_NOTFOUND; +} +#endif + +static int fdt_set_busfreq(void *fdt, int nodeoffset, const char *name, bd_t *bd) +{ + u32 tmp; + /* + * Create or update the property. + */ + tmp = cpu_to_be32(bd->bi_busfreq); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/* * Fixups to the fdt. If "create" is TRUE, the node is created * unconditionally. If "create" is FALSE, the node is updated * only if it already exists. */ -#define FT_UPDATE 0x00000000 /* update existing property only */ -#define FT_CREATE 0x00000001 /* create property if it doesn't exist */ -#define FT_BUSFREQ 0x00000002 /* source is bd->bi_busfreq */ -#define FT_ENETADDR 0x00000004 /* source is bd->bi_enetaddr */ static const struct { - int createflags; char *node; char *prop; + int (*set_fn)(void *fdt, int nodeoffset, const char *name, bd_t *bd); } fixup_props[] = { - { FT_CREATE | FT_BUSFREQ, - "/cpus/" OF_CPU, + { "/cpus/" OF_CPU, "bus-frequency", + fdt_set_busfreq }, - { FT_CREATE | FT_BUSFREQ, - "/cpus/" OF_SOC, - "bus-frequency" + { "/cpus/" OF_SOC, + "bus-frequency", + fdt_set_busfreq }, - { FT_CREATE | FT_BUSFREQ, - "/" OF_SOC "/serial@4500/", - "clock-frequency" + { "/" OF_SOC "/serial@4500/", + "clock-frequency", + fdt_set_busfreq }, - { FT_CREATE | FT_BUSFREQ, - "/" OF_SOC "/serial@4600/", - "clock-frequency" + { "/" OF_SOC "/serial@4600/", + "clock-frequency", + fdt_set_busfreq }, #ifdef CONFIG_MPC83XX_TSEC1 - { FT_UPDATE | FT_ENETADDR, - "/" OF_SOC "/ethernet@24000, + { "/" OF_SOC "/ethernet@24000, "mac-address", + fdt_set_eth0 }, - { FT_UPDATE | FT_ENETADDR, - "/" OF_SOC "/ethernet@24000, + { "/" OF_SOC "/ethernet@24000, "local-mac-address", + fdt_set_eth0 }, #endif #ifdef CONFIG_MPC83XX_TSEC2 - { FT_UPDATE | FT_ENETADDR, - "/" OF_SOC "/ethernet@25000, + { "/" OF_SOC "/ethernet@25000, + "mac-address", + fdt_set_eth1 + }, + { "/" OF_SOC "/ethernet@25000, + "local-mac-address", + fdt_set_eth1 + }, +#endif +#ifdef CONFIG_UEC_ETH1 +#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ + { "/" OF_QE "/ucc@2000/mac-address", + "mac-address", + fdt_set_eth0 + }, + { "/" OF_QE "/ucc@2000/mac-address", + "local-mac-address", + fdt_set_eth0 + }, +#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */ + { "/" OF_QE "/ucc@2200/mac-address", + "mac-address", + fdt_set_eth0 + }, + { "/" OF_QE "/ucc@2200/mac-address", + "local-mac-address", + fdt_set_eth0 + }, +#endif +#endif +#ifdef CONFIG_UEC_ETH2 +#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */ + { "/" OF_QE "/ucc@3000/mac-address", "mac-address", + fdt_set_eth1 }, - { FT_UPDATE | FT_ENETADDR, - "/" OF_SOC "/ethernet@25000, + { "/" OF_QE "/ucc@3000/mac-address", "local-mac-address", + fdt_set_eth1 + }, +#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */ + { "/" OF_QE "/ucc@3200/mac-address", + "mac-address", + fdt_set_eth1 }, + { "/" OF_QE "/ucc@3200/mac-address", + "local-mac-address", + fdt_set_eth1 + }, +#endif #endif }; void ft_cpu_setup(void *blob, bd_t *bd) { - int nodeoffset; - int err; - int j; + int nodeoffset; + int err; + int j; for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) { - nodeoffset = fdt_path_offset (fdt, fixup_props[j].node); + nodeoffset = fdt_path_offset(fdt, fixup_props[j].node); if (nodeoffset >= 0) { - /* - * If unconditional create or the property already exists... - */ - if ((fixup_props[j].createflags & FT_CREATE) || - (fdt_get_property(fdt, nodeoffset, fixup_props[j].prop, 0))) { - if (fixup_props[j].createflags & FT_BUSFREQ) { - u32 tmp; - - tmp = cpu_to_be32(bd->bi_busfreq); - err = fdt_setprop(fdt, nodeoffset, - fixup_props[j].prop, &tmp, sizeof(tmp)); - } else if (fixup_props[j].createflags & FT_ENETADDR) { - err = fdt_setprop(fdt, nodeoffset, - fixup_props[j].prop, bd->bi_enetaddr, 6); - } else { - printf("ft_cpu_setup: %s %s has no flag for the value to set\n", - fixup_props[j].node, - fixup_props[j].prop); - } - if (err < 0) - printf("libfdt: %s %s returned %s\n", - fixup_props[j].node, - fixup_props[j].prop, - fdt_strerror(err)); - } + err = (*fixup_props[j].set_fn)(blob, nodeoffset, fixup_props[j].prop, bd); + if (err < 0) + printf("set_fn/libfdt: %s %s returned %s\n", + fixup_props[j].node, + fixup_props[j].prop, + fdt_strerror(err)); } } } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 551b243076..84f5bef508 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,12 +32,6 @@ #include <ft_build.h> #endif -#ifdef CONFIG_MPC8641HPCN -extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[]); -#endif - - int checkcpu(void) { @@ -185,7 +179,7 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #else /* CONFIG_MPC8641HPCN */ - mpc8641_reset_board(cmdtp, flag, argc, argv); + out8(PIXIS_BASE + PIXIS_RST, 0); #endif /* !CONFIG_MPC8641HPCN */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index b56629bf57..2ecd3e4b61 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -1124,7 +1124,7 @@ static void program_codt(unsigned long *dimm_populated, modt3 = 0x00000000; } } - } else { + } else { codt |= SDRAM_CODT_DQS_2_5_V_DDR1; modt0 = 0x00000000; modt1 = 0x00000000; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3b1586c0ae..a96083caa5 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1892,11 +1892,11 @@ pll_wait: #endif /* CONFIG_405EP */ #if defined(CONFIG_440) -#define function_prolog(func_name) .text; \ +#define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ func_name: -#define function_epilog(func_name) .type func_name,@function; \ +#define function_epilog(func_name) .type func_name,@function; \ .size func_name,.-func_name /*----------------------------------------------------------------------------+ @@ -1952,13 +1952,13 @@ pll_wait: +----------------------------------------------------------------------------*/ function_prolog(dcbz_area) rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 sync blr function_epilog(dcbz_area) @@ -1967,26 +1967,26 @@ pll_wait: | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag sync - mtmsr r9 + mtmsr r9 blr function_epilog(dflush) #endif /* CONFIG_440 */ diff --git a/disk/part.c b/disk/part.c index 9e8bd4fb88..acc1a748e4 100644 --- a/disk/part.c +++ b/disk/part.c @@ -179,6 +179,7 @@ void dev_print (block_dev_desc_t *dev_desc) #if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) #if defined(CONFIG_MAC_PARTITION) || \ diff --git a/doc/README.NetConsole b/doc/README.NetConsole index cc35a0a8ff..fea8e33646 100644 --- a/doc/README.NetConsole +++ b/doc/README.NetConsole @@ -38,6 +38,11 @@ The script expects exactly one argument, which is interpreted as the target IP address (or host name, assuming DNS is working). The script can be interrupted by pressing ^T (CTRL-T). +Be aware that in some distributives (Fedora Core 5 at least) +usage of nc has been changed and -l and -p options are considered +as mutually exclusive. If nc complains about options provided, +you can just remove the -p option from the script. + It turns out that 'netcat' cannot be used to listen to broadcast packets. We developed our own tool 'ncb' (see tools directory) that listens to broadcast packets on a given port and dumps them to the diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 new file mode 100644 index 0000000000..8659e83673 --- /dev/null +++ b/doc/README.mpc7448hpc2 @@ -0,0 +1,184 @@ +Freescale MPC7448hpc2 (Taiga) board +=================================== + +Created 08/11/2006 Roy Zang +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX +chassis. + +Building U-Boot +------------------ +The mpc7448hpc2 code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make mpc7448hpc2_config + Configuring for mpc7448hpc2 board... + + $ make + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + +Board Switches +---------------------- + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 4a650ce43c..3b88f8bc72 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -121,3 +121,37 @@ To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M 0xfe00_0000 0xfeff_ffff Flash(alternate)16M 0xff00_0000 0xffff_ffff Flash(boot bank)16M + +5. pixis_reset command +-------------------- +A new command, "pixis_reset", is introduced to reset mpc8641hpcn board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + +Valid clock choices are in the 8641 Reference Manuals. diff --git a/drivers/Makefile b/drivers/Makefile index fffc22a5e1..d68cba682b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -32,7 +32,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o \ i8042.o inca-ip_sw.o keyboard.o \ - lan91c96.o \ + lan91c96.o macb.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ @@ -46,6 +46,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ status_led.o sym53c8xx.o systemace.o ahci.o \ ti_pci1410a.o tigon3.o tsec.o \ + tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ videomodes.o w83c553f.o \ ks8695eth.o \ diff --git a/drivers/atmel_usart.c b/drivers/atmel_usart.c index 41c37683d7..f35b99730f 100644 --- a/drivers/atmel_usart.c +++ b/drivers/atmel_usart.c @@ -19,7 +19,22 @@ #ifdef CONFIG_ATMEL_USART #include <asm/io.h> -#include <asm/arch/platform.h> +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> + +#if defined(CONFIG_USART0) +# define USART_ID 0 +# define USART_BASE USART0_BASE +#elif defined(CONFIG_USART1) +# define USART_ID 1 +# define USART_BASE USART1_BASE +#elif defined(CONFIG_USART2) +# define USART_ID 2 +# define USART_BASE USART2_BASE +#elif defined(CONFIG_USART3) +# define USART_ID 3 +# define USART_BASE USART3_BASE +#endif #include "atmel_usart.h" @@ -35,26 +50,23 @@ void serial_setbrg(void) * Baud Rate = -------------- * 16 * CD */ - usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id); + usart_hz = get_usart_clk_rate(USART_ID); divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; - usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor)); + usart3_writel(BRGR, USART3_BF(CD, divisor)); } int serial_init(void) { - usart3_writel(gd->console_uart, CR, - USART3_BIT(RSTRX) | USART3_BIT(RSTTX)); + usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX)); serial_setbrg(); - usart3_writel(gd->console_uart, CR, - USART3_BIT(RXEN) | USART3_BIT(TXEN)); - usart3_writel(gd->console_uart, MR, - USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) - | USART3_BF(USCLKS, USART3_USCLKS_MCK) - | USART3_BF(CHRL, USART3_CHRL_8) - | USART3_BF(PAR, USART3_PAR_NONE) - | USART3_BF(NBSTOP, USART3_NBSTOP_1)); + usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN)); + usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) + | USART3_BF(USCLKS, USART3_USCLKS_MCK) + | USART3_BF(CHRL, USART3_CHRL_8) + | USART3_BF(PAR, USART3_PAR_NONE) + | USART3_BF(NBSTOP, USART3_NBSTOP_1))); return 0; } @@ -64,8 +76,8 @@ void serial_putc(char c) if (c == '\n') serial_putc('\r'); - while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(TXRDY))) ; - usart3_writel(gd->console_uart, THR, c); + while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ; + usart3_writel(THR, c); } void serial_puts(const char *s) @@ -76,13 +88,13 @@ void serial_puts(const char *s) int serial_getc(void) { - while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY))) ; - return usart3_readl(gd->console_uart, RHR); + while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) ; + return usart3_readl(RHR); } int serial_tstc(void) { - return (usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY)) != 0; + return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0; } #endif /* CONFIG_ATMEL_USART */ diff --git a/drivers/atmel_usart.h b/drivers/atmel_usart.h index fad90a8116..af3773a99f 100644 --- a/drivers/atmel_usart.h +++ b/drivers/atmel_usart.h @@ -306,9 +306,9 @@ | USART3_BF(name,value)) /* Register access macros */ -#define usart3_readl(port,reg) \ - readl((port)->regs + USART3_##reg) -#define usart3_writel(port,reg,value) \ - writel((value), (port)->regs + USART3_##reg) +#define usart3_readl(reg) \ + readl((void *)USART_BASE + USART3_##reg) +#define usart3_writel(reg,value) \ + writel((value), (void *)USART_BASE + USART3_##reg) #endif /* __DRIVERS_ATMEL_USART_H__ */ diff --git a/drivers/macb.c b/drivers/macb.c new file mode 100644 index 0000000000..186ab19d35 --- /dev/null +++ b/drivers/macb.c @@ -0,0 +1,575 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <common.h> + +#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII)) + +/* + * The u-boot networking stack is a little weird. It seems like the + * networking core allocates receive buffers up front without any + * regard to the hardware that's supposed to actually receive those + * packets. + * + * The MACB receives packets into 128-byte receive buffers, so the + * buffers allocated by the core isn't very practical to use. We'll + * allocate our own, but we need one such buffer in case a packet + * wraps around the DMA ring so that we have to copy it. + * + * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific + * configuration header. This way, the core allocates one RX buffer + * and one TX buffer, each of which can hold a ethernet packet of + * maximum size. + * + * For some reason, the networking core unconditionally specifies a + * 32-byte packet "alignment" (which really should be called + * "padding"). MACB shouldn't need that, but we'll refrain from any + * core modifications here... + */ + +#include <net.h> +#include <malloc.h> + +#include <linux/mii.h> +#include <asm/io.h> +#include <asm/dma-mapping.h> +#include <asm/arch/clk.h> + +#include "macb.h" + +#define CFG_MACB_RX_BUFFER_SIZE 4096 +#define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128) +#define CFG_MACB_TX_RING_SIZE 16 +#define CFG_MACB_TX_TIMEOUT 1000 +#define CFG_MACB_AUTONEG_TIMEOUT 5000000 + +struct macb_dma_desc { + u32 addr; + u32 ctrl; +}; + +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 + +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 + +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 + +struct macb_device { + void *regs; + + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; + + unsigned long rx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; + + const struct device *dev; + struct eth_device netdev; + unsigned short phy_addr; +}; +#define to_macb(_nd) container_of(_nd, struct macb_device, netdev) + +static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); +} + +static u16 macb_mdio_read(struct macb_device *macb, u8 reg) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); + + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + frame = macb_readl(macb, MAN); + + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + + return MACB_BFEXT(DATA, frame); +} + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +static int macb_send(struct eth_device *netdev, volatile void *packet, + int length) +{ + struct macb_device *macb = to_macb(netdev); + unsigned long paddr, ctrl; + unsigned int tx_head = macb->tx_head; + int i; + + paddr = dma_map_single(packet, length, DMA_TO_DEVICE); + + ctrl = length & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) { + ctrl |= TXBUF_WRAP; + macb->tx_head = 0; + } else + macb->tx_head++; + + macb->tx_ring[tx_head].ctrl = ctrl; + macb->tx_ring[tx_head].addr = paddr; + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); + + /* + * I guess this is necessary because the networking core may + * re-use the transmit buffer as soon as we return... + */ + i = 0; + while (!(macb->tx_ring[tx_head].ctrl & TXBUF_USED)) { + if (i > CFG_MACB_TX_TIMEOUT) { + printf("%s: TX timeout\n", netdev->name); + break; + } + udelay(1); + i++; + } + + dma_unmap_single(packet, length, paddr); + + if (i <= CFG_MACB_TX_TIMEOUT) { + ctrl = macb->tx_ring[tx_head].ctrl; + if (ctrl & TXBUF_UNDERRUN) + printf("%s: TX underrun\n", netdev->name); + if (ctrl & TXBUF_EXHAUSTED) + printf("%s: TX buffers exhausted in mid frame\n", + netdev->name); + } + + /* No one cares anyway */ + return 0; +} + +static void reclaim_rx_buffers(struct macb_device *macb, + unsigned int new_tail) +{ + unsigned int i; + + i = macb->rx_tail; + while (i > new_tail) { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > CFG_MACB_RX_RING_SIZE) + i = 0; + } + + while (i < new_tail) { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } + + macb->rx_tail = new_tail; +} + +static int macb_recv(struct eth_device *netdev) +{ + struct macb_device *macb = to_macb(netdev); + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int length; + int wrapped = 0; + u32 status; + + for (;;) { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + return -1; + + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } + + if (status & RXBUF_FRAME_END) { + buffer = macb->rx_buffer + 128 * macb->rx_tail; + length = status & RXBUF_FRMLEN_MASK; + if (wrapped) { + unsigned int headlen, taillen; + + headlen = 128 * (CFG_MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = length - headlen; + memcpy((void *)NetRxPackets[0], + buffer, headlen); + memcpy((void *)NetRxPackets[0] + headlen, + macb->rx_buffer, taillen); + buffer = (void *)NetRxPackets[0]; + } + + NetReceive(buffer, length); + if (++rx_tail >= CFG_MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + } else { + if (++rx_tail >= CFG_MACB_RX_RING_SIZE) { + wrapped = 1; + rx_tail = 0; + } + } + } + + return 0; +} + +static int macb_phy_init(struct macb_device *macb) +{ + struct eth_device *netdev = &macb->netdev; + u32 ncfgr; + u16 phy_id, status, adv, lpa; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) { + printf("%s: No PHY present\n", netdev->name); + return 0; + } + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + printf("%s: Starting autonegotiation...\n", netdev->name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); + +#if 0 + for (i = 0; i < 9; i++) + printf("mii%d: 0x%04x\n", i, macb_mdio_read(macb, i)); +#endif + + for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } + + if (status & BMSR_ANEGCOMPLETE) + printf("%s: Autonegotiation complete\n", netdev->name); + else + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + netdev->name, status); + + if (!(status & BMSR_LSTATUS)) { + for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { + udelay(100); + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down (status: 0x%04x)\n", + netdev->name, status); + return 0; + } else { + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + netdev->name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } +} + +static int macb_init(struct eth_device *netdev, bd_t *bd) +{ + struct macb_device *macb = to_macb(netdev); + unsigned long paddr; + u32 hwaddr_bottom; + u16 hwaddr_top; + int i; + + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ + + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) { + if (i == (CFG_MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) { + macb->tx_ring[i].addr = 0; + if (i == (CFG_MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); + + /* set hardware address */ + hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + /* choose RMII or MII mode. This depends on the board */ +#ifdef CONFIG_RMII + macb_writel(macb, USRIO, 0); +#else + macb_writel(macb, USRIO, MACB_BIT(MII)); +#endif + + if (!macb_phy_init(macb)) + return 0; + + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); + + return 1; +} + +static void macb_halt(struct eth_device *netdev) +{ + struct macb_device *macb = to_macb(netdev); + u32 ncr, tsr; + + /* Halt the controller and wait for any ongoing transmission to end. */ + ncr = macb_readl(macb, NCR); + ncr |= MACB_BIT(THALT); + macb_writel(macb, NCR, ncr); + + do { + tsr = macb_readl(macb, TSR); + } while (tsr & MACB_BIT(TGO)); + + /* Disable TX and RX, and clear statistics */ + macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); +} + +int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) +{ + struct macb_device *macb; + struct eth_device *netdev; + unsigned long macb_hz; + u32 ncfgr; + + macb = malloc(sizeof(struct macb_device)); + if (!macb) { + printf("Error: Failed to allocate memory for MACB%d\n", id); + return -1; + } + memset(macb, 0, sizeof(struct macb_device)); + + netdev = &macb->netdev; + + macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE, + &macb->rx_buffer_dma); + macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE + * sizeof(struct macb_dma_desc), + &macb->rx_ring_dma); + macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE + * sizeof(struct macb_dma_desc), + &macb->tx_ring_dma); + + macb->regs = regs; + macb->phy_addr = phy_addr; + + sprintf(netdev->name, "macb%d", id); + netdev->init = macb_init; + netdev->halt = macb_halt; + netdev->send = macb_send; + netdev->recv = macb_recv; + + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = get_macb_pclk_rate(id); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + + macb_writel(macb, NCFGR, ncfgr); + + eth_register(netdev); + + return 0; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_MII) + +int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + int iflag; + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl |= MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(&macb, EMACB_MAN, frame); + + do { + netstat = macb_readl(&macb, EMACB_NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + frame = macb_readl(&macb, EMACB_MAN); + *value = MACB_BFEXT(DATA, frame); + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + return 0; +} + +int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) +{ + unsigned long netctl; + unsigned long netstat; + unsigned long frame; + int iflag; + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl |= MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(&macb, EMACB_MAN, frame); + + do { + netstat = macb_readl(&macb, EMACB_NSR); + } while (!(netstat & MACB_BIT(IDLE))); + + iflag = disable_interrupts(); + netctl = macb_readl(&macb, EMACB_NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(&macb, EMACB_NCR, netctl); + if (iflag) + enable_interrupts(); + + return 0; +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#endif /* CONFIG_MACB */ diff --git a/drivers/macb.h b/drivers/macb.h new file mode 100644 index 0000000000..c778e4ee49 --- /dev/null +++ b/drivers/macb.h @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __DRIVERS_MACB_H__ +#define __DRIVERS_MACB_H__ + +/* MACB register offsets */ +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 + +/* Bitfields in NCR */ +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 + +/* Bitfields in NCFGR */ +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 + +/* Bitfields in NSR */ +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 + +/* Bitfields in TSR */ +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 + +/* Bitfields in RSR */ +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 + +/* Bitfields in ISR/IER/IDR/IMR */ +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 + +/* Bitfields in MAN */ +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 + +/* Bitfields in USRIO */ +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 + +/* Bitfields in WOL */ +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 + +/* Constants for CLK */ +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 + +/* Constants for MAN register */ +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 + +/* Bit manipulation macros */ +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) +#define MACB_BFEXT(name,value)\ + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) + +/* Register access macros */ +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) + +#endif /* __DRIVERS_MACB_H__ */ diff --git a/drivers/tsi108_eth.c b/drivers/tsi108_eth.c new file mode 100644 index 0000000000..47341bee7f --- /dev/null +++ b/drivers/tsi108_eth.c @@ -0,0 +1,1036 @@ +/*********************************************************************** + * + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * Ethernet interface for Tundra TSI108 bridge chip + * + ***********************************************************************/ + +#include <config.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_TSI108_ETH) + +#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2) +#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2" +#endif + +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/cache.h> + +#ifdef DEBUG +#define TSI108_ETH_DEBUG 7 +#else +#define TSI108_ETH_DEBUG 0 +#endif + +#if TSI108_ETH_DEBUG > 0 +#define debug_lev(lev, fmt, args...) \ +if (lev <= TSI108_ETH_DEBUG) \ +printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) +#else +#define debug_lev(lev, fmt, args...) do{}while(0) +#endif + +#define RX_PRINT_ERRORS +#define TX_PRINT_ERRORS + +#define ETH_BASE (CFG_TSI108_CSR_BASE + 0x6000) + +#define ETH_PORT_OFFSET 0x400 + +#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) + +#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) +#define MAC_CONFIG_1_TX_ENABLE (0x00000001) +#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002) +#define MAC_CONFIG_1_RX_ENABLE (0x00000004) +#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008) +#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010) +#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020) +#define MAC_CONFIG_1_LOOP_BACK (0x00000100) +#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000) +#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000) +#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000) +#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000) +#define MAC_CONFIG_1_SIM_RESET (0x40000000) +#define MAC_CONFIG_1_SOFT_RESET (0x80000000) + +#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) +#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001) +#define MAC_CONFIG_2_CRC_ENABLE (0x00000002) +#define MAC_CONFIG_2_PAD_CRC (0x00000004) +#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010) +#define MAC_CONFIG_2_HUGE_FRAME (0x00000020) +#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8) +#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12) +#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */ +#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */ + +#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) + +#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) +#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7) +#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010) +#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020) +#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000) + +#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) +#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001) +#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002) + +#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) +#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) +#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) + +#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) +#define MII_MGMT_INDICATORS_BUSY (0x00000001) +#define MII_MGMT_INDICATORS_SCAN (0x00000002) +#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004) + +#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c) +#define INTERFACE_STATUS_LINK_FAIL (0x00000008) +#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200) + +#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040) +#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044) + +#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200) +#define PORT_CONTROL_PRI (0x00000001) +#define PORT_CONTROL_BPT (0x00010000) +#define PORT_CONTROL_SPD (0x00040000) +#define PORT_CONTROL_RBC (0x00080000) +#define PORT_CONTROL_PRB (0x00200000) +#define PORT_CONTROL_DIS (0x00400000) +#define PORT_CONTROL_TBI (0x00800000) +#define PORT_CONTROL_STE (0x10000000) +#define PORT_CONTROL_ZOR (0x20000000) +#define PORT_CONTROL_CLR (0x40000000) +#define PORT_CONTROL_SRT (0x80000000) + +#define reg_TX_CONFIG(base) __REG32(base, 0x00000220) +#define TX_CONFIG_START_Q (0x00000003) +#define TX_CONFIG_EHP (0x00400000) +#define TX_CONFIG_CHP (0x00800000) +#define TX_CONFIG_RST (0x80000000) + +#define reg_TX_CONTROL(base) __REG32(base, 0x00000224) +#define TX_CONTROL_GO (0x00008000) +#define TX_CONTROL_MP (0x01000000) +#define TX_CONTROL_EAI (0x20000000) +#define TX_CONTROL_ABT (0x40000000) +#define TX_CONTROL_EII (0x80000000) + +#define reg_TX_STATUS(base) __REG32(base, 0x00000228) +#define TX_STATUS_QUEUE_USABLE (0x0000000f) +#define TX_STATUS_CURR_Q (0x00000300) +#define TX_STATUS_ACT (0x00008000) +#define TX_STATUS_QUEUE_IDLE (0x000f0000) +#define TX_STATUS_EOQ_PENDING (0x0f000000) + +#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c) +#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f) +#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00) +#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) +#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) + +#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230) + +#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270) +#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) +#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000) +#define TX_DIAGNOSTIC_ADDR_AI (0x80000000) + +#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274) + +#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278) +#define TX_ERROR_STATUS (0x00000278) +#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010) +#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020) +#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040) +#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080) +#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000) +#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000) +#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000) +#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000) +#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000) +#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000) +#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000) + +#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280) +#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) +#define TX_QUEUE_0_CONFIG_BSWP (0x00000400) +#define TX_QUEUE_0_CONFIG_WSWP (0x00000800) +#define TX_QUEUE_0_CONFIG_AM (0x00004000) +#define TX_QUEUE_0_CONFIG_GVI (0x00008000) +#define TX_QUEUE_0_CONFIG_EEI (0x00010000) +#define TX_QUEUE_0_CONFIG_ELI (0x00020000) +#define TX_QUEUE_0_CONFIG_ENI (0x00040000) +#define TX_QUEUE_0_CONFIG_ESI (0x00080000) +#define TX_QUEUE_0_CONFIG_EDI (0x00100000) + +#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284) +#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) +#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) +#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) +#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) + +#define OCN_PORT_HLP 0 /* HLP Interface */ +#define OCN_PORT_PCI_X 1 /* PCI-X Interface */ +#define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */ +#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */ +#define OCN_PORT_MEMORY 4 /* Memory Controller */ +#define OCN_PORT_DMA 5 /* DMA Controller */ +#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */ +#define OCN_PORT_PRINT 7 /* Print Engine Interface */ + +#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288) + +#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c) +#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000) + +#define reg_RX_CONFIG(base) __REG32(base, 0x00000320) +#define RX_CONFIG_DEF_Q (0x00000003) +#define RX_CONFIG_EMF (0x00000100) +#define RX_CONFIG_EUF (0x00000200) +#define RX_CONFIG_BFE (0x00000400) +#define RX_CONFIG_MFE (0x00000800) +#define RX_CONFIG_UFE (0x00001000) +#define RX_CONFIG_SE (0x00002000) +#define RX_CONFIG_ABF (0x00200000) +#define RX_CONFIG_APE (0x00400000) +#define RX_CONFIG_CHP (0x00800000) +#define RX_CONFIG_RST (0x80000000) + +#define reg_RX_CONTROL(base) __REG32(base, 0x00000324) +#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f) +#define GE_E0_RX_CONTROL_GO (0x00008000) +#define GE_E0_RX_CONTROL_EAI (0x20000000) +#define GE_E0_RX_CONTROL_ABT (0x40000000) +#define GE_E0_RX_CONTROL_EII (0x80000000) + +#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c) +#define RX_EXTENDED_STATUS (0x0000032c) +#define RX_EXTENDED_STATUS_EOQ (0x0000000f) +#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001) +#define RX_EXTENDED_STATUS_EOF (0x00000f00) +#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000) +#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000) + +#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330) + +#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370) +#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f) +#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000) +#define RX_DIAGNOSTIC_ADDR_AI (0x80000000) + +#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374) + +#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380) +#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f) +#define RX_QUEUE_0_CONFIG_BSWP (0x00000400) +#define RX_QUEUE_0_CONFIG_WSWP (0x00000800) +#define RX_QUEUE_0_CONFIG_AM (0x00004000) +#define RX_QUEUE_0_CONFIG_EEI (0x00010000) +#define RX_QUEUE_0_CONFIG_ELI (0x00020000) +#define RX_QUEUE_0_CONFIG_ENI (0x00040000) +#define RX_QUEUE_0_CONFIG_ESI (0x00080000) +#define RX_QUEUE_0_CONFIG_EDI (0x00100000) + +#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384) +#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f) +#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300) +#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400) +#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800) + +#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388) + +#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c) +#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000) + +/* + * PHY register definitions + */ +/* the first 15 PHY registers are standard. */ +#define PHY_CTRL_REG 0 /* Control Register */ +#define PHY_STATUS_REG 1 /* Status Regiser */ +#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */ +#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */ +#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */ +#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */ + +/* + * PHY Register bit masks. + */ +#define PHY_CTRL_RESET (1 << 15) +#define PHY_CTRL_LOOPBACK (1 << 14) +#define PHY_CTRL_SPEED0 (1 << 13) +#define PHY_CTRL_AN_EN (1 << 12) +#define PHY_CTRL_PWR_DN (1 << 11) +#define PHY_CTRL_ISOLATE (1 << 10) +#define PHY_CTRL_RESTART_AN (1 << 9) +#define PHY_CTRL_FULL_DUPLEX (1 << 8) +#define PHY_CTRL_CT_EN (1 << 7) +#define PHY_CTRL_SPEED1 (1 << 6) + +#define PHY_STAT_100BASE_T4 (1 << 15) +#define PHY_STAT_100BASE_X_FD (1 << 14) +#define PHY_STAT_100BASE_X_HD (1 << 13) +#define PHY_STAT_10BASE_T_FD (1 << 12) +#define PHY_STAT_10BASE_T_HD (1 << 11) +#define PHY_STAT_100BASE_T2_FD (1 << 10) +#define PHY_STAT_100BASE_T2_HD (1 << 9) +#define PHY_STAT_EXT_STAT (1 << 8) +#define PHY_STAT_RESERVED (1 << 7) +#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */ +#define PHY_STAT_AN_COMPLETE (1 << 5) +#define PHY_STAT_REM_FAULT (1 << 4) +#define PHY_STAT_AN_CAP (1 << 3) +#define PHY_STAT_LINK_UP (1 << 2) +#define PHY_STAT_JABBER (1 << 1) +#define PHY_STAT_EXT_CAP (1 << 0) + +#define TBI_CONTROL_2 0x11 +#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001 +#define TBI_CONTROL_2_ENABLE_WRAP 0x0002 +#define TBI_CONTROL_2_G_MII_MODE 0x0010 +#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020 +#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100 +#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000 +#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000 +#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000 +#define TBI_CONTROL_2_SOFT_RESET 0x8000 + +/* marvel specific */ +#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */ +#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */ +#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */ + +/* + * MARVELL 88E1111 PHY register bit masks + */ +/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */ + +#define SPEC_STAT_SPEED_MASK (3 << 14) +#define SPEC_STAT_FULL_DUP (1 << 13) +#define SPEC_STAT_PAGE_RCVD (1 << 12) +#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */ +#define SPEC_STAT_LINK_UP (1 << 10) +#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */ +#define SPEC_STAT_MDIX (1 << 6) +#define SPEC_STAT_POLARITY (1 << 1) +#define SPEC_STAT_JABBER (1 << 0) + +#define SPEED_1000 (2 << 14) +#define SPEED_100 (1 << 14) +#define SPEED_10 (0 << 14) + +#define TBI_ADDR 0x1E /* Ten Bit Interface address */ + +/* negotiated link parameters */ +#define LINK_SPEED_UNKNOWN 0 +#define LINK_SPEED_10 1 +#define LINK_SPEED_100 2 +#define LINK_SPEED_1000 3 + +#define LINK_DUPLEX_UNKNOWN 0 +#define LINK_DUPLEX_HALF 1 +#define LINK_DUPLEX_FULL 2 + +static unsigned int phy_address[] = { 8, 9 }; + +#define vuint32 volatile u32 + +/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte) + * This structure is accessed by the ethernet DMA engine which means it + * MUST be in LITTLE ENDIAN format */ +struct dma_descriptor { + vuint32 start_addr0; /* buffer address, least significant bytes. */ + vuint32 start_addr1; /* buffer address, most significant bytes. */ + vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */ + vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */ + vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */ + vuint32 config_status; /* Configuration/Status. */ + vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */ + vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */ +}; + +/* last next descriptor address flag */ +#define DMA_DESCR_LAST (1 << 31) + +/* TX DMA descriptor config status bits */ +#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */ +#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */ +#define DMA_DESCR_TX_PFVLAN (1 << 2) +#define DMA_DESCR_TX_HUGE (1 << 3) +#define DMA_DESCR_TX_PAD (1 << 4) +#define DMA_DESCR_TX_CRC (1 << 5) +#define DMA_DESCR_TX_DESCR_INT (1 << 14) +#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000 +#define DMA_DESCR_TX_ONE_COLLISION (1 << 20) +#define DMA_DESCR_TX_LATE_COLLISION (1 << 24) +#define DMA_DESCR_TX_UNDERRUN (1 << 25) +#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26) +#define DMA_DESCR_TX_OK (1 << 30) +#define DMA_DESCR_TX_OWNER (1 << 31) + +/* RX DMA descriptor status bits */ +#define DMA_DESCR_RX_EOF (1 << 0) +#define DMA_DESCR_RX_SOF (1 << 1) +#define DMA_DESCR_RX_VTF (1 << 2) +#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3) +#define DMA_DESCR_RX_SHORT_FRAME (1 << 4) +#define DMA_DESCR_RX_HASH_MATCH (1 << 7) +#define DMA_DESCR_RX_BAD_FRAME (1 << 8) +#define DMA_DESCR_RX_OVERRUN (1 << 9) +#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11) +#define DMA_DESCR_RX_CRC_ERROR (1 << 12) +#define DMA_DESCR_RX_DESCR_INT (1 << 13) +#define DMA_DESCR_RX_OWNER (1 << 15) + +#define RX_BUFFER_SIZE PKTSIZE +#define NUM_RX_DESC PKTBUFSRX + +static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32))); + +static struct dma_descriptor rx_descr_array[NUM_RX_DESC] + __attribute__ ((aligned(32))); + +static struct dma_descriptor *rx_descr_current; + +static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis); +static int tsi108_eth_send (struct eth_device *dev, + volatile void *packet, int length); +static int tsi108_eth_recv (struct eth_device *dev); +static void tsi108_eth_halt (struct eth_device *dev); +static unsigned int read_phy (unsigned int base, + unsigned int phy_addr, unsigned int phy_reg); +static void write_phy (unsigned int base, + unsigned int phy_addr, + unsigned int phy_reg, unsigned int phy_data); + +#if TSI108_ETH_DEBUG > 100 +/* + * print phy debug infomation + */ +static void dump_phy_regs (unsigned int phy_addr) +{ + int i; + + printf ("PHY %d registers\n", phy_addr); + for (i = 0; i <= 30; i++) { + printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i)); + } + printf ("\n"); + +} +#else +#define dump_phy_regs(base) do{}while(0) +#endif + +#if TSI108_ETH_DEBUG > 100 +/* + * print debug infomation + */ +static void tx_diag_regs (unsigned int base) +{ + int i; + unsigned long dummy; + + printf ("TX diagnostics registers\n"); + reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_TX_DIAGNOSTIC_DATA(base); + for (i = 0x00; i <= 0x05; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); + } + reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_TX_DIAGNOSTIC_DATA(base); + for (i = 0x40; i <= 0x47; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base)); + } + printf ("\n"); + +} +#else +#define tx_diag_regs(base) do{}while(0) +#endif + +#if TSI108_ETH_DEBUG > 100 +/* + * print debug infomation + */ +static void rx_diag_regs (unsigned int base) +{ + int i; + unsigned long dummy; + + printf ("RX diagnostics registers\n"); + reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_RX_DIAGNOSTIC_DATA(base); + for (i = 0x00; i <= 0x05; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); + } + reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI; + udelay (1000); + dummy = reg_RX_DIAGNOSTIC_DATA(base); + for (i = 0x08; i <= 0x0a; i++) { + udelay (1000); + printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base)); + } + printf ("\n"); + +} +#else +#define rx_diag_regs(base) do{}while(0) +#endif + +#if TSI108_ETH_DEBUG > 100 +/* + * print debug infomation + */ +static void debug_mii_regs (unsigned int base) +{ + printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base)); + printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base)); + printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base)); + printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base)); + printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base)); + printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base)); + printf ("\n"); + +} +#else +#define debug_mii_regs(base) do{}while(0) +#endif + +/* + * Wait until the phy bus is non-busy + */ +static void phy_wait (unsigned int base, unsigned int condition) +{ + int timeout; + + timeout = 0; + while (reg_MII_MGMT_INDICATORS(base) & condition) { + udelay (10); + if (++timeout > 10000) { + printf ("ERROR: timeout waiting for phy bus (%d)\n", + condition); + break; + } + } +} + +/* + * read phy register + */ +static unsigned int read_phy (unsigned int base, + unsigned int phy_addr, unsigned int phy_reg) +{ + unsigned int value; + + phy_wait (base, MII_MGMT_INDICATORS_BUSY); + + reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; + + /* Ensure that the Read Cycle bit is cleared prior to next read cycle */ + reg_MII_MGMT_COMMAND(base) = 0; + + /* start the read */ + reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE; + + /* wait for the read to complete */ + phy_wait (base, + MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY); + + value = reg_MII_MGMT_STATUS(base); + + reg_MII_MGMT_COMMAND(base) = 0; + + return value; +} + +/* + * write phy register + */ +static void write_phy (unsigned int base, + unsigned int phy_addr, + unsigned int phy_reg, unsigned int phy_data) +{ + phy_wait (base, MII_MGMT_INDICATORS_BUSY); + + reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg; + + /* Ensure that the Read Cycle bit is cleared prior to next cycle */ + reg_MII_MGMT_COMMAND(base) = 0; + + /* start the write */ + reg_MII_MGMT_CONTROL(base) = phy_data; +} + +/* + * configure the marvell 88e1111 phy + */ +static int marvell_88e_phy_config (struct eth_device *dev, int *speed, + int *duplex) +{ + unsigned long base; + unsigned long phy_addr; + unsigned int phy_status; + unsigned int phy_spec_status; + int timeout; + int phy_speed; + int phy_duplex; + unsigned int value; + + phy_speed = LINK_SPEED_UNKNOWN; + phy_duplex = LINK_DUPLEX_UNKNOWN; + + base = dev->iobase; + phy_addr = (unsigned long)dev->priv; + + /* Take the PHY out of reset. */ + write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET); + + /* Wait for the reset process to complete. */ + udelay (10); + timeout = 0; + while ((phy_status = + read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) { + udelay (10); + if (++timeout > 10000) { + printf ("ERROR: timeout waiting for phy reset\n"); + break; + } + } + + /* TBI Configuration. */ + write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE | + TBI_CONTROL_2_RECEIVE_CLOCK_SELECT); + /* Wait for the link to be established. */ + timeout = 0; + do { + udelay (20000); + phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG); + if (++timeout > 100) { + debug_lev(1, "ERROR: unable to establish link!!!\n"); + break; + } + } while ((phy_status & PHY_STAT_LINK_UP) == 0); + + if ((phy_status & PHY_STAT_LINK_UP) == 0) + return 0; + + value = 0; + phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); + if (phy_spec_status & SPEC_STAT_RESOLVED) { + switch (phy_spec_status & SPEC_STAT_SPEED_MASK) { + case SPEED_1000: + phy_speed = LINK_SPEED_1000; + value |= PHY_CTRL_SPEED1; + break; + case SPEED_100: + phy_speed = LINK_SPEED_100; + value |= PHY_CTRL_SPEED0; + break; + case SPEED_10: + phy_speed = LINK_SPEED_10; + break; + } + if (phy_spec_status & SPEC_STAT_FULL_DUP) { + phy_duplex = LINK_DUPLEX_FULL; + value |= PHY_CTRL_FULL_DUPLEX; + } else + phy_duplex = LINK_DUPLEX_HALF; + } + /* set TBI speed */ + write_phy (base, TBI_ADDR, PHY_CTRL_REG, value); + write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060); + +#if TSI108_ETH_DEBUG > 0 + printf ("%s link is up", dev->name); + phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG); + if (phy_spec_status & SPEC_STAT_RESOLVED) { + switch (phy_speed) { + case LINK_SPEED_1000: + printf (", 1000 Mbps"); + break; + case LINK_SPEED_100: + printf (", 100 Mbps"); + break; + case LINK_SPEED_10: + printf (", 10 Mbps"); + break; + } + if (phy_duplex == LINK_DUPLEX_FULL) + printf (", Full duplex"); + else + printf (", Half duplex"); + } + printf ("\n"); +#endif + + dump_phy_regs (TBI_ADDR); + if (speed) + *speed = phy_speed; + if (duplex) + *duplex = phy_duplex; + + return 1; +} + +/* + * External interface + * + * register the tsi108 ethernet controllers with the multi-ethernet system + */ +int tsi108_eth_initialize (bd_t * bis) +{ + struct eth_device *dev; + int index; + + for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) { + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + + sprintf (dev->name, "TSI108_eth%d", index); + + dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); + dev->priv = (void *)(phy_address[index]); + dev->init = tsi108_eth_probe; + dev->halt = tsi108_eth_halt; + dev->send = tsi108_eth_send; + dev->recv = tsi108_eth_recv; + + eth_register(dev); + } + return index; +} + +/* + * probe for and initialize a single ethernet interface + */ +static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) +{ + unsigned long base; + unsigned long value; + int index; + struct dma_descriptor *tx_descr; + struct dma_descriptor *rx_descr; + int speed; + int duplex; + + base = dev->iobase; + + reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT; + + /* Bring DMA/FIFO out of reset. */ + reg_TX_CONFIG(base) = 0x00000000; + reg_RX_CONFIG(base) = 0x00000000; + + reg_TX_THRESHOLDS(base) = (192 << 16) | 192; + reg_RX_THRESHOLDS(base) = (192 << 16) | 112; + + /* Bring MAC out of reset. */ + reg_MAC_CONFIG_1(base) = 0x00000000; + + /* DMA MAC configuration. */ + reg_MAC_CONFIG_1(base) = + MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE; + + reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE; + reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE; + + /* Note: Early tsi108 manual did not have correct byte order + * for the station address.*/ + reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) | + (dev->enetaddr[4] << 16) | + (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0); + + reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) | + (dev->enetaddr[0] << 16); + + if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) + return 0; + + value = + MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | + MAC_CONFIG_2_CRC_ENABLE; + if (speed == LINK_SPEED_1000) + value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE); + else { + value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE); + reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD; + } + if (duplex == LINK_DUPLEX_FULL) { + value |= MAC_CONFIG_2_FULL_DUPLEX; + reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT; + } else + reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT; + reg_MAC_CONFIG_2(base) = value; + + reg_RX_CONFIG(base) = RX_CONFIG_SE; + reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; + reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; + + /* initialize the RX DMA descriptors */ + rx_descr = &rx_descr_array[0]; + rx_descr_current = rx_descr; + for (index = 0; index < NUM_RX_DESC; index++) { + /* make sure the receive buffers are not in cache */ + invalidate_dcache_range((unsigned long)NetRxPackets[index], + (unsigned long)NetRxPackets[index] + + RX_BUFFER_SIZE); + rx_descr->start_addr0 = + cpu_to_le32((vuint32) NetRxPackets[index]); + rx_descr->start_addr1 = 0; + rx_descr->next_descr_addr0 = + cpu_to_le32((vuint32) (rx_descr + 1)); + rx_descr->next_descr_addr1 = 0; + rx_descr->vlan_byte_count = 0; + rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) | + DMA_DESCR_RX_OWNER); + rx_descr++; + } + rx_descr--; + rx_descr->next_descr_addr0 = 0; + rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); + /* Push the descriptors to RAM so the ethernet DMA can see them */ + invalidate_dcache_range((unsigned long)rx_descr_array, + (unsigned long)rx_descr_array + + sizeof(rx_descr_array)); + + /* enable RX queue */ + reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01; + reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current; + /* enable receive DMA */ + reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; + + reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY; + reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY; + + /* initialize the TX DMA descriptor */ + tx_descr = &tx_descriptor; + + tx_descr->start_addr0 = 0; + tx_descr->start_addr1 = 0; + tx_descr->next_descr_addr0 = 0; + tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); + tx_descr->vlan_byte_count = 0; + tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK | + DMA_DESCR_TX_SOF | + DMA_DESCR_TX_EOF); + /* enable TX queue */ + reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; + + return 1; +} + +/* + * send a packet + */ +static int tsi108_eth_send (struct eth_device *dev, + volatile void *packet, int length) +{ + unsigned long base; + int timeout; + struct dma_descriptor *tx_descr; + unsigned long status; + + base = dev->iobase; + tx_descr = &tx_descriptor; + + /* Wait until the last packet has been transmitted. */ + timeout = 0; + do { + /* make sure we see the changes made by the DMA engine */ + invalidate_dcache_range((unsigned long)tx_descr, + (unsigned long)tx_descr + + sizeof(struct dma_descriptor)); + + if (timeout != 0) + udelay (15); + if (++timeout > 10000) { + tx_diag_regs(base); + debug_lev(1, + "ERROR: timeout waiting for last transmit packet to be sent\n"); + return 0; + } + } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER)); + + status = le32_to_cpu(tx_descr->config_status); + if ((status & DMA_DESCR_TX_OK) == 0) { +#ifdef TX_PRINT_ERRORS + printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status, + status & DMA_DESCR_TX_OK ? "tx error, " : "", + status & DMA_DESCR_TX_RETRY_LIMIT ? + "retry limit reached, " : "", + status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "", + status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, " + : ""); +#endif + } + + debug_lev (9, "sending packet %d\n", length); + tx_descr->start_addr0 = cpu_to_le32((vuint32) packet); + tx_descr->start_addr1 = 0; + tx_descr->next_descr_addr0 = 0; + tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST); + tx_descr->vlan_byte_count = cpu_to_le32(length); + tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER | + DMA_DESCR_TX_CRC | + DMA_DESCR_TX_PAD | + DMA_DESCR_TX_SOF | + DMA_DESCR_TX_EOF); + + invalidate_dcache_range((unsigned long)tx_descr, + (unsigned long)tx_descr + + sizeof(struct dma_descriptor)); + + invalidate_dcache_range((unsigned long)packet, + (unsigned long)packet + length); + + reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr; + reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID; + + return length; +} + +/* + * Check for received packets and send them up the protocal stack + */ +static int tsi108_eth_recv (struct eth_device *dev) +{ + struct dma_descriptor *rx_descr; + unsigned long base; + int length = 0; + unsigned long status; + volatile uchar *buffer; + + base = dev->iobase; + + /* make sure we see the changes made by the DMA engine */ + invalidate_dcache_range ((unsigned long)rx_descr_array, + (unsigned long)rx_descr_array + + sizeof(rx_descr_array)); + + /* process all of the received packets */ + rx_descr = rx_descr_current; + while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) { + /* check for error */ + status = le32_to_cpu(rx_descr->config_status); + if (status & DMA_DESCR_RX_BAD_FRAME) { +#ifdef RX_PRINT_ERRORS + printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n", + status, + status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, " + : "", + status & DMA_DESCR_RX_SHORT_FRAME ? "too short, " + : "", + status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " : + "", + status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "", + status & DMA_DESCR_RX_MAX_FRAME_LEN ? + "max length, " : "", + status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " : + ""); +#endif + } else { + length = + le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF; + + /*** process packet ***/ + buffer = + (volatile uchar + *)(le32_to_cpu (rx_descr->start_addr0)); + NetReceive (buffer, length); + + invalidate_dcache_range ((unsigned long)buffer, + (unsigned long)buffer + + RX_BUFFER_SIZE); + } + /* Give this buffer back to the DMA engine */ + rx_descr->vlan_byte_count = 0; + rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) | + DMA_DESCR_RX_OWNER); + /* move descriptor pointer forward */ + rx_descr = + (struct dma_descriptor + *)(le32_to_cpu (rx_descr->next_descr_addr0)); + if (rx_descr == 0) + rx_descr = &rx_descr_array[0]; + } + /* remember where we are for next time */ + rx_descr_current = rx_descr; + + /* If the DMA engine has reached the end of the queue + * start over at the begining */ + if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) { + + reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0; + reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0]; + reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID; + } + + return length; +} + +/* + * disable an ethernet interface + */ +static void tsi108_eth_halt (struct eth_device *dev) +{ + unsigned long base; + + base = dev->iobase; + + /* Put DMA/FIFO into reset state. */ + reg_TX_CONFIG(base) = TX_CONFIG_RST; + reg_RX_CONFIG(base) = RX_CONFIG_RST; + + /* Put MAC into reset state. */ + reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET; +} + +#endif diff --git a/drivers/tsi108_i2c.c b/drivers/tsi108_i2c.c new file mode 100644 index 0000000000..eb52cb66c9 --- /dev/null +++ b/drivers/tsi108_i2c.c @@ -0,0 +1,283 @@ +/* + * (C) Copyright 2004 Tundra Semiconductor Corp. + * Author: Alex Bounine + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <config.h> +#include <common.h> + +#ifdef CONFIG_TSI108_I2C +#include <tsi108.h> + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + +#define I2C_DELAY 100000 +#undef DEBUG_I2C + +#ifdef DEBUG_I2C +#define DPRINT(x) printf (x) +#else +#define DPRINT(x) +#endif + +/* All functions assume that Tsi108 I2C block is the only master on the bus */ +/* I2C read helper function */ + +static int i2c_read_byte ( + uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */ + uchar chip_addr,/* I2C device address on the bus */ + uint byte_addr, /* Byte address within I2C device */ + uchar * buffer /* pointer to data buffer */ + ) +{ + u32 temp; + u32 to_count = I2C_DELAY; + u32 op_status = TSI108_I2C_TIMEOUT_ERR; + u32 chan_offset = TSI108_I2C_OFFSET; + + DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n", + i2c_chan, chip_addr, byte_addr)); + + if (0 != i2c_chan) + chan_offset = TSI108_I2C_SDRAM_OFFSET; + + /* Check if I2C operation is in progress */ + temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); + + if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | + I2C_CNTRL2_START))) { + /* Set device address and operation (read = 0) */ + temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | + ((chip_addr >> 3) & 0x0F); + *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = + temp; + + /* Issue the read command + * (at this moment all other parameters are 0 + * (size = 1 byte, lane = 0) + */ + + *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = + (I2C_CNTRL2_START); + + /* Wait until operation completed */ + do { + /* Read I2C operation status */ + temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); + + if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) { + if (0 == (temp & + (I2C_CNTRL2_I2C_CFGERR | + I2C_CNTRL2_I2C_TO_ERR)) + ) { + op_status = TSI108_I2C_SUCCESS; + + temp = *(u32 *) (CFG_TSI108_CSR_BASE + + chan_offset + + I2C_RD_DATA); + + *buffer = (u8) (temp & 0xFF); + } else { + /* report HW error */ + op_status = TSI108_I2C_IF_ERROR; + + DPRINT (("I2C HW error reported: 0x%02x\n", temp)); + } + + break; + } + } while (to_count--); + } else { + op_status = TSI108_I2C_IF_BUSY; + + DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); + } + + DPRINT (("I2C read_byte() status: 0x%02x\n", op_status)); + return op_status; +} + +/* + * I2C Read interface as defined in "include/i2c.h" : + * chip_addr: I2C chip address, range 0..127 + * (to read from SPD channel EEPROM use (0xD0 ... 0xD7) + * NOTE: The bit 7 in the chip_addr serves as a channel select. + * This hack is for enabling "isdram" command on Tsi108 boards + * without changes to common code. Used for I2C reads only. + * byte_addr: Memory or register address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Pointer to destination buffer for data to be read + * len: How many bytes to read + * + * Returns: 0 on success, not 0 on failure + */ + +int i2c_read (uchar chip_addr, uint byte_addr, int alen, + uchar * buffer, int len) +{ + u32 op_status = TSI108_I2C_PARAM_ERR; + u32 i2c_if = 0; + + /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/ + if (0xD0 == (chip_addr & ~0x07)) { + i2c_if = 1; + chip_addr &= 0x7F; + } + /* Check for valid I2C address */ + if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { + while (len--) { + op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++); + + if (TSI108_I2C_SUCCESS != op_status) { + DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); + + break; + } + } + } + + DPRINT (("I2C read() status: 0x%02x\n", op_status)); + return op_status; +} + +/* I2C write helper function */ + +static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ + uint byte_addr, /* Byte address within I2C device */ + uchar * buffer /* pointer to data buffer */ + ) +{ + u32 temp; + u32 to_count = I2C_DELAY; + u32 op_status = TSI108_I2C_TIMEOUT_ERR; + + /* Check if I2C operation is in progress */ + temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); + + if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { + /* Place data into the I2C Tx Register */ + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_TX_DATA) = (u32) * buffer; + + /* Set device address and operation */ + temp = + I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | + ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_CNTRL1) = temp; + + /* Issue the write command (at this moment all other parameters + * are 0 (size = 1 byte, lane = 0) + */ + + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + I2C_CNTRL2) = (I2C_CNTRL2_START); + + op_status = TSI108_I2C_TIMEOUT_ERR; + + /* Wait until operation completed */ + do { + /* Read I2C operation status */ + temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); + + if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { + if (0 == (temp & + (I2C_CNTRL2_I2C_CFGERR | + I2C_CNTRL2_I2C_TO_ERR))) { + op_status = TSI108_I2C_SUCCESS; + } else { + /* report detected HW error */ + op_status = TSI108_I2C_IF_ERROR; + + DPRINT (("I2C HW error reported: 0x%02x\n", temp)); + } + + break; + } + + } while (to_count--); + } else { + op_status = TSI108_I2C_IF_BUSY; + + DPRINT (("I2C Transaction start failed: 0x%02x\n", temp)); + } + + return op_status; +} + +/* + * I2C Write interface as defined in "include/i2c.h" : + * chip_addr: I2C chip address, range 0..127 + * byte_addr: Memory or register address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Pointer to data to be written + * len: How many bytes to write + * + * Returns: 0 on success, not 0 on failure + */ + +int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer, + int len) +{ + u32 op_status = TSI108_I2C_PARAM_ERR; + + /* Check for valid I2C address */ + if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { + while (len--) { + op_status = + i2c_write_byte (chip_addr, byte_addr++, buffer++); + + if (TSI108_I2C_SUCCESS != op_status) { + DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len)); + + break; + } + } + } + + return op_status; +} + +/* + * I2C interface function as defined in "include/i2c.h". + * Probe the given I2C chip address by reading single byte from offset 0. + * Returns 0 if a chip responded, not 0 on failure. + */ + +int i2c_probe (uchar chip) +{ + u32 tmp; + + /* + * Try to read the first location of the chip. + * The Tsi108 HW doesn't support sending just the chip address + * and checkong for an <ACK> back. + */ + return i2c_read (chip, 0, 1, (char *)&tmp, 1); +} + +#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */ +#endif /* CONFIG_TSI108_I2C */ diff --git a/drivers/tsi108_pci.c b/drivers/tsi108_pci.c new file mode 100644 index 0000000000..9f606df518 --- /dev/null +++ b/drivers/tsi108_pci.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2004 Tundra Semiconductor Corp. + * Alex Bounine <alexandreb@tundra.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI initialisation for the Tsi108 EMU board. + */ + +#include <config.h> + +#ifdef CONFIG_TSI108_PCI + +#include <common.h> +#include <pci.h> +#include <asm/io.h> +#include <tsi108.h> + +struct pci_controller local_hose; + +void tsi108_clear_pci_error (void) +{ + u32 err_stat, err_addr, pci_stat; + + /* + * Quietly clear errors signalled as result of PCI/X configuration read + * requests. + */ + /* Read PB Error Log Registers */ + err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE + + TSI108_PB_REG_OFFSET + PB_ERRCS); + err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE + + TSI108_PB_REG_OFFSET + PB_AERR); + if (err_stat & PB_ERRCS_ES) { + /* Clear PCI/X bus errors if applicable */ + if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) { + /* Clear error flag */ + *(u32 *) (CFG_TSI108_CSR_BASE + + TSI108_PB_REG_OFFSET + PB_ERRCS) = + PB_ERRCS_ES; + + /* Clear read error reported in PB_ISR */ + *(u32 *) (CFG_TSI108_CSR_BASE + + TSI108_PB_REG_OFFSET + PB_ISR) = + PB_ISR_PBS_RD_ERR; + + /* Clear errors reported by PCI CSR (Normally Master Abort) */ + pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + + PCI_CSR); + *(volatile u32 *)(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_CSR) = + pci_stat; + + *(volatile u32 *)(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + + PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR; + } + } + + return; +} + +unsigned int __get_pci_config_dword (u32 addr) +{ + unsigned int retval; + + __asm__ __volatile__ (" lwbrx %0,0,%1\n" + "1: eieio\n" + "2:\n" + ".section .fixup,\"ax\"\n" + "3: li %0,-1\n" + " b 2b\n" + ".section __ex_table,\"a\"\n" + " .align 2\n" + " .long 1b,3b\n" + ".text":"=r"(retval):"r"(addr)); + + return (retval); +} + +static int tsi108_read_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 * value) +{ + dev &= (CFG_PCI_CFG_SIZE - 1); + dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); + *value = __get_pci_config_dword(dev); + if (0xFFFFFFFF == *value) + tsi108_clear_pci_error (); + return 0; +} + +static int tsi108_write_config_dword (struct pci_controller *hose, + pci_dev_t dev, int offset, u32 value) +{ + dev &= (CFG_PCI_CFG_SIZE - 1); + dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); + + out_le32 ((volatile unsigned *)dev, value); + + return 0; +} + +void pci_init_board (void) +{ + struct pci_controller *hose = (struct pci_controller *)&local_hose; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region (hose->regions + 1, + CFG_PCI_MEM_BUS, + CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region (hose->regions + 2, + CFG_PCI_IO_BUS, + CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + + hose->region_count = 3; + + pci_set_ops (hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + tsi108_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + tsi108_write_config_dword); + + pci_register_hose (hose); + + hose->last_busno = pci_hose_scan (hose); + + debug ("Done PCI initialization\n"); + return; +} + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup (void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop (blob, "/" OF_TSI "/pci@1000/bus-range", &len); + if (p != NULL) { + p[0] = local_hose.first_busno; + p[1] = local_hose.last_busno; + } + +} +#endif + +#endif /* CONFIG_TSI108_PCI */ diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 33e396a066..ba73bae9e5 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -111,7 +111,7 @@ typedef enum __cpu_t { CPU_750CX, CPU_750FX, CPU_750GX, CPU_7400, CPU_7410, - CPU_7448, + CPU_7447A, CPU_7448, CPU_7450, CPU_7455, CPU_7457, CPU_UNKNOWN} cpu_t; diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h new file mode 100644 index 0000000000..7e20d97b7f --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/clk.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CLK_H__ +#define __ASM_AVR32_ARCH_CLK_H__ + +#ifdef CONFIG_PLL +#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#else +#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#endif + +static inline unsigned long get_cpu_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; +} +static inline unsigned long get_hsb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; +} +static inline unsigned long get_pba_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; +} +static inline unsigned long get_pbb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; +} + +/* Accessors for specific devices. More will be added as needed. */ +static inline unsigned long get_sdram_clk_rate(void) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return get_pbb_clk_rate(); +} +static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_mci_clk_rate(void) +{ + return get_pbb_clk_rate(); +} + +#endif /* __ASM_AVR32_ARCH_CLK_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/gpio.h b/include/asm-avr32/arch-at32ap7000/gpio.h new file mode 100644 index 0000000000..e4812d4d08 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/gpio.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_GPIO_H__ +#define __ASM_AVR32_ARCH_GPIO_H__ + +#include <asm/arch/memory-map.h> + +#define NR_GPIO_CONTROLLERS 5 + +/* + * Pin numbers identifying specific GPIO pins on the chip. + */ +#define GPIO_PIOA_BASE (0) +#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) +#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) +#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) +#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) +#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) +#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) +#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) +#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) +#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) +#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) +#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) +#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) +#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) +#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) +#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) +#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) +#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) +#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) +#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) +#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) +#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) +#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) +#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) +#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) +#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) +#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) +#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) +#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) +#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) +#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) +#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) +#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) + +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) +#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) +#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) +#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) +#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) +#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) +#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) +#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) +#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) +#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) +#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) +#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) +#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) +#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) +#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) +#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) +#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) +#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) +#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) +#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) +#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) +#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) +#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) +#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) +#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) +#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) +#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) +#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) +#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) +#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) +#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) +#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) + +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) +#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) +#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) +#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) +#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) +#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) +#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) +#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) +#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) +#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) +#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) +#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) +#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) +#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) +#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) +#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) +#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) +#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) +#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) +#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) +#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) +#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) +#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) +#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) +#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) +#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) +#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) +#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) +#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) +#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) +#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) +#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) +#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) + +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) +#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) +#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) +#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) +#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) +#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) +#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) +#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) +#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) +#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) +#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) +#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) +#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) +#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) +#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) +#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) +#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) +#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) + +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) +#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) +#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) +#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) +#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) +#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) +#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) +#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) +#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) +#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) +#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) +#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) +#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) +#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) +#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) +#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) +#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) +#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) +#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) +#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) +#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) +#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) +#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) +#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) +#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) +#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) +#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) +#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) + +static inline void *gpio_pin_to_addr(unsigned int pin) +{ + switch (pin >> 5) { + case 0: + return (void *)PIOA_BASE; + case 1: + return (void *)PIOB_BASE; + case 2: + return (void *)PIOC_BASE; + case 3: + return (void *)PIOD_BASE; + case 4: + return (void *)PIOE_BASE; + default: + return NULL; + } +} + +void gpio_select_periph_A(unsigned int pin, int use_pullup); +void gpio_select_periph_B(unsigned int pin, int use_pullup); + +void gpio_enable_ebi(void); +void gpio_enable_usart0(void); +void gpio_enable_usart1(void); +void gpio_enable_usart2(void); +void gpio_enable_usart3(void); +void gpio_enable_macb0(void); +void gpio_enable_macb1(void); +void gpio_enable_mmci(void); + +#endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h index e6df4b7fe3..b0e787a92f 100644 --- a/include/asm-avr32/arch-at32ap7000/hmatrix2.h +++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h @@ -224,9 +224,9 @@ | HMATRIX2_BF(name,value)) /* Register access macros */ -#define hmatrix2_readl(port,reg) \ - readl((port)->regs + HMATRIX2_##reg) -#define hmatrix2_writel(port,reg,value) \ - writel((value), (port)->regs + HMATRIX2_##reg) +#define hmatrix2_readl(reg) \ + readl((void *)HMATRIX_BASE + HMATRIX2_##reg) +#define hmatrix2_writel(reg,value) \ + writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) #endif /* __ASM_AVR32_HMATRIX2_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h index 8ffe851c89..5513e88e7b 100644 --- a/include/asm-avr32/arch-at32ap7000/memory-map.h +++ b/include/asm-avr32/arch-at32ap7000/memory-map.h @@ -19,43 +19,48 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__ -#define __ASM_AVR32_PART_MEMORY_MAP_H__ +#ifndef __AT32AP7000_MEMORY_MAP_H__ +#define __AT32AP7000_MEMORY_MAP_H__ -#define AUDIOC_BASE 0xFFF02800 -#define DAC_BASE 0xFFF02000 -#define DMAC_BASE 0xFF200000 -#define ECC_BASE 0xFFF03C00 -#define HISI_BASE 0xFFF02C00 -#define HMATRIX_BASE 0xFFF00800 -#define HSDRAMC_BASE 0xFFF03800 -#define HSMC_BASE 0xFFF03400 -#define LCDC_BASE 0xFF000000 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define MMCI_BASE 0xFFF02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 -#define PWM_BASE 0xFFF01400 -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0XFFF00400 -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define USB_FIFO 0xFF300000 -#define USB_BASE 0xFFF03000 +/* Devices on the High Speed Bus (HSB) */ +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 -#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */ +/* Devices on Peripheral Bus A (PBA) */ +#define SPI0_BASE 0xFFE00000 +#define SPI1_BASE 0xFFE00400 +#define TWI_BASE 0xFFE00800 +#define USART0_BASE 0xFFE00C00 +#define USART1_BASE 0xFFE01000 +#define USART2_BASE 0xFFE01400 +#define USART3_BASE 0xFFE01800 +#define SSC0_BASE 0xFFE01C00 +#define SSC1_BASE 0xFFE02000 +#define SSC2_BASE 0xFFE02400 +#define PIOA_BASE 0xFFE02800 +#define PIOB_BASE 0xFFE02C00 +#define PIOC_BASE 0xFFE03000 +#define PIOD_BASE 0xFFE03400 +#define PIOE_BASE 0xFFE03800 +#define PSIF_BASE 0xFFE03C00 + +/* Devices on Peripheral Bus B (PBB) */ +#define SM_BASE 0xFFF00000 +#define INTC_BASE 0xFFF00400 +#define HMATRIX_BASE 0xFFF00800 +#define TIMER0_BASE 0xFFF00C00 +#define TIMER1_BASE 0xFFF01000 +#define PWM_BASE 0xFFF01400 +#define MACB0_BASE 0xFFF01800 +#define MACB1_BASE 0xFFF01C00 +#define DAC_BASE 0xFFF02000 +#define MMCI_BASE 0xFFF02400 +#define AUDIOC_BASE 0xFFF02800 +#define HISI_BASE 0xFFF02C00 +#define USB_BASE 0xFFF03000 +#define HSMC_BASE 0xFFF03400 +#define HSDRAMC_BASE 0xFFF03800 +#define ECC_BASE 0xFFF03C00 + +#endif /* __AT32AP7000_MEMORY_MAP_H__ */ diff --git a/include/asm-avr32/arch-at32ap7000/mmc.h b/include/asm-avr32/arch-at32ap7000/mmc.h new file mode 100644 index 0000000000..fcfbbb3c6c --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/mmc.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_MMC_H +#define __ASM_AVR32_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AVR32_MMC_H */ diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h deleted file mode 100644 index 759050116a..0000000000 --- a/include/asm-avr32/arch-at32ap7000/platform.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_AVR32_ARCH_PM_H -#define _ASM_AVR32_ARCH_PM_H - -#include <config.h> - -enum clock_domain_id { - CLOCK_CPU, - CLOCK_HSB, - CLOCK_PBA, - CLOCK_PBB, - NR_CLOCK_DOMAINS, -}; - -enum resource_type { - RESOURCE_GPIO, - RESOURCE_CLOCK, -}; - -enum gpio_func { - GPIO_FUNC_GPIO, - GPIO_FUNC_A, - GPIO_FUNC_B, -}; - -enum device_id { - DEVICE_HEBI, - DEVICE_PBA_BRIDGE, - DEVICE_PBB_BRIDGE, - DEVICE_HRAMC, - /* GPIO controllers must be kept together */ - DEVICE_PIOA, - DEVICE_PIOB, - DEVICE_PIOC, - DEVICE_PIOD, - DEVICE_PIOE, - DEVICE_SM, - DEVICE_INTC, - DEVICE_HMATRIX, -#if defined(CFG_HPDC) - DEVICE_HPDC, -#endif -#if defined(CFG_MACB0) - DEVICE_MACB0, -#endif -#if defined(CFG_MACB1) - DEVICE_MACB1, -#endif -#if defined(CFG_LCDC) - DEVICE_LCDC, -#endif -#if defined(CFG_USART0) - DEVICE_USART0, -#endif -#if defined(CFG_USART1) - DEVICE_USART1, -#endif -#if defined(CFG_USART2) - DEVICE_USART2, -#endif -#if defined(CFG_USART3) - DEVICE_USART3, -#endif -#if defined(CFG_MMCI) - DEVICE_MMCI, -#endif -#if defined(CFG_DMAC) - DEVICE_DMAC, -#endif - NR_DEVICES, - NO_DEVICE = -1, -}; - -struct resource { - enum resource_type type; - union { - struct { - unsigned long base; - } iomem; - struct { - unsigned char nr_pins; - enum device_id gpio_dev; - enum gpio_func func; - unsigned short start; - } gpio; - struct { - enum clock_domain_id id; - unsigned char index; - } clock; - } u; -}; - -struct device { - void *regs; - unsigned int nr_resources; - const struct resource *resource; -}; - -struct clock_domain { - unsigned short reg; - enum clock_domain_id id; - enum device_id bridge; -}; - -extern const struct device chip_device[NR_DEVICES]; -extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS]; - -/** - * Set up PIO, clock management and I/O memory for a device. - */ -const struct device *get_device(enum device_id devid); -void put_device(const struct device *dev); - -int gpio_set_func(enum device_id gpio_devid, unsigned int start, - unsigned int nr_pins, enum gpio_func func); -void gpio_free(enum device_id gpio_devid, unsigned int start, - unsigned int nr_pins); - -void pm_init(void); -int pm_enable_clock(enum clock_domain_id id, unsigned int index); -void pm_disable_clock(enum clock_domain_id id, unsigned int index); -unsigned long pm_get_clock_freq(enum clock_domain_id domain); - -void cpu_enable_sdram(void); - -#endif /* _ASM_AVR32_ARCH_PM_H */ diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index 01d836c639..681c514ccf 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -35,10 +35,8 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - const struct device *console_uart; - const struct device *sm; unsigned long baudrate; - unsigned long sdram_size; + unsigned long stack_end; /* highest stack address */ unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of env struct */ diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h index 7ba25cde53..583e5dc101 100644 --- a/include/asm-avr32/initcalls.h +++ b/include/asm-avr32/initcalls.h @@ -26,8 +26,6 @@ extern int cpu_init(void); extern int timer_init(void); -extern void board_init_memories(void); -extern void board_init_pio(void); extern void board_init_info(void); #endif /* __ASM_AVR32_INITCALLS_H__ */ diff --git a/include/asm-blackfin/arch-bf533/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h index ce58863b10..65749ee458 100644 --- a/include/asm-blackfin/arch-bf533/bf533_serial.h +++ b/include/asm-blackfin/arch-bf533/bf533_serial.h @@ -1,7 +1,7 @@ /* * U-boot bf533_serial.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_SERIAL_H_ diff --git a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h index bc09922a5e..f4440a8d47 100644 --- a/include/asm-blackfin/arch-bf533/bf5xx_rtc.h +++ b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h @@ -1,7 +1,7 @@ /* * U-boot - bf533_rtc.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_RTC_H_ diff --git a/include/asm-blackfin/arch-bf533/cplbtab.h b/include/asm-blackfin/arch-bf533/cplbtab.h deleted file mode 100644 index 89f0325381..0000000000 --- a/include/asm-blackfin/arch-bf533/cplbtab.h +++ /dev/null @@ -1,482 +0,0 @@ -/*This file is subject to the terms and conditions of the GNU General Public - * License. - * - * Blackfin BF533/2.6 support : LG Soft India - * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd - * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's - * shouldn't be victimized. cplbmgr.S search logic is corrected - * to findout the appropriate victim. - * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC - * : LG Soft India - */ -#include <config.h> - -#ifndef __ARCH_BFINNOMMU_CPLBTAB_H -#define __ARCH_BFINNOMMU_CPLBTAB_H - -/************************************************************************* - * ICPLB TABLE - *************************************************************************/ - -.data -/* This table is configurable */ - .align 4; - -/* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) -#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) - -#else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) -#endif - -.align 4; -.global _ipdt_table _ipdt_table:.byte4 0x00000000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ -#ifndef CONFIG_EZKIT /*STAMP Memory regions */ -.byte4 0x02000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ -#endif -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ - -#ifdef CONFIG_STAMP -.byte4 0x04000000; -.byte4(SDRAM_IGENERIC); -.byte4 0x04400000; -.byte4(SDRAM_IGENERIC); -.byte4 0x04800000; -.byte4(SDRAM_IGENERIC); -.byte4 0x04C00000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05000000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05400000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05800000; -.byte4(SDRAM_IGENERIC); -.byte4 0x05C00000; -.byte4(SDRAM_IGENERIC); -.byte4 0x06000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */ -.byte4 0x06400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */ -.byte4 0x06800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */ -.byte4 0x06C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */ -.byte4 0x07000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */ -.byte4 0x07400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */ -.byte4 0x07800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */ -.byte4 0x07C00000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */ -#endif -.byte4 0xffffffff; /* end of section - termination */ - -/********************************************************************** - * PAGE DESCRIPTOR TABLE - * - **********************************************************************/ - -/* Till here we are discussing about the static memory management model. - * However, the operating envoronments commonly define more CPLB - * descriptors to cover the entire addressable memory than will fit into - * the available on-chip 16 CPLB MMRs. When this happens, the below table - * will be used which will hold all the potentially required CPLB descriptors - * - * This is how Page descriptor Table is implemented in uClinux/Blackfin. - */ -.global _dpdt_table _dpdt_table:.byte4 0x00000000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ - -#ifndef CONFIG_EZKIT -.byte4 0x02000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ -#endif - -#ifdef CONFIG_STAMP -.byte4 0x04000000; -.byte4(SDRAM_DGENERIC); -.byte4 0x04400000; -.byte4(SDRAM_DGENERIC); -.byte4 0x04800000; -.byte4(SDRAM_DGENERIC); -.byte4 0x04C00000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05000000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05400000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05800000; -.byte4(SDRAM_DGENERIC); -.byte4 0x05C00000; -.byte4(SDRAM_DGENERIC); -.byte4 0x06000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */ -.byte4 0x06400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */ -.byte4 0x06800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */ -.byte4 0x06C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */ -.byte4 0x07000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */ -.byte4 0x07400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */ -.byte4 0x07800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */ -.byte4 0x07C00000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */ -#endif - -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ - -#if (BFIN_CPU == ADSP_BF533) -.byte4 0xFF800000; -.byte4(L1_DMEMORY); -.byte4 0xFF801000; -.byte4(L1_DMEMORY); -.byte4 0xFF802000; -.byte4(L1_DMEMORY); -.byte4 0xFF803000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFF804000; -.byte4(L1_DMEMORY); -.byte4 0xFF805000; -.byte4(L1_DMEMORY); -.byte4 0xFF806000; -.byte4(L1_DMEMORY); -.byte4 0xFF807000; -.byte4(L1_DMEMORY); -#if (BFIN_CPU == ADSP_BF533) -.byte4 0xFF900000; -.byte4(L1_DMEMORY); -.byte4 0xFF901000; -.byte4(L1_DMEMORY); -.byte4 0xFF902000; -.byte4(L1_DMEMORY); -.byte4 0xFF903000; -.byte4(L1_DMEMORY); -#endif -#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533)) -.byte4 0xFF904000; -.byte4(L1_DMEMORY); -.byte4 0xFF905000; -.byte4(L1_DMEMORY); -.byte4 0xFF906000; -.byte4(L1_DMEMORY); -.byte4 0xFF907000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFFB00000; -.byte4(L1_DMEMORY); - -.byte4 0xffffffff; /*end of section - termination */ - -#ifdef CONFIG_CPLB_INFO -.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ -_ipdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 90 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ - -.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ -_dpdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 110 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 120 */ -#endif - -#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/arch-bf533/irq.h b/include/asm-blackfin/arch-bf533/irq.h index 9c5230db41..323574590b 100644 --- a/include/asm-blackfin/arch-bf533/irq.h +++ b/include/asm-blackfin/arch-bf533/irq.h @@ -1,7 +1,7 @@ /* * U-boot bf533_irq.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c @@ -33,8 +33,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_IRQ_H_ diff --git a/include/asm-blackfin/arch-bf537/bf537_serial.h b/include/asm-blackfin/arch-bf537/bf537_serial.h index 1610411ee9..64088f243c 100644 --- a/include/asm-blackfin/arch-bf537/bf537_serial.h +++ b/include/asm-blackfin/arch-bf537/bf537_serial.h @@ -1,7 +1,7 @@ /* * U-boot bf537_serial.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF537_SERIAL_H_ diff --git a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h index 0043e42bf2..db5cc6f226 100644 --- a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h +++ b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h @@ -1,7 +1,7 @@ /* * U-boot - bf537_rtc.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF537_RTC_H_ diff --git a/include/asm-blackfin/arch-bf537/cplbtab.h b/include/asm-blackfin/arch-bf537/cplbtab.h deleted file mode 100644 index c5151bb4ab..0000000000 --- a/include/asm-blackfin/arch-bf537/cplbtab.h +++ /dev/null @@ -1,408 +0,0 @@ -/*This file is subject to the terms and conditions of the GNU General Public - * License. - * - * Blackfin BF533/2.6 support : LG Soft India - * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd - * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's - * shouldn't be victimized. cplbmgr.S search logic is corrected - * to findout the appropriate victim. - * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC - * : LG Soft India - */ -#include <config.h> - -#ifndef __ARCH_BFINNOMMU_CPLBTAB_H -#define __ARCH_BFINNOMMU_CPLBTAB_H - -/* - * ICPLB TABLE - */ - -.data -/* This table is configurable */ - .align 4; - -/* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) -#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) - -/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ - -#define ANOMALY_05000158 0x200 -#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) - -#else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) -#endif - -.align 4; -.global _ipdt_table _ipdt_table:.byte4 0x00000000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ -.byte4 0x02000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ - -.byte4 0xffffffff; /* end of section - termination */ - -/* - * PAGE DESCRIPTOR TABLE - * - */ - -/* - * Till here we are discussing about the static memory management model. - * However, the operating envoronments commonly define more CPLB - * descriptors to cover the entire addressable memory than will fit into - * the available on-chip 16 CPLB MMRs. When this happens, the below table - * will be used which will hold all the potentially required CPLB descriptors - * - * This is how Page descriptor Table is implemented in uClinux/Blackfin. - */ -.global _dpdt_table _dpdt_table:.byte4 0x00000000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ -.byte4 0x00400000; -.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ -.byte4 0x00800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ -.byte4 0x00C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ -.byte4 0x01000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ -.byte4 0x01400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ -.byte4 0x01800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ -.byte4 0x01C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ -.byte4 0x02000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ -.byte4 0x02400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ -.byte4 0x02800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ -.byte4 0x02C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ -.byte4 0x03000000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ -.byte4 0x03400000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ -.byte4 0x03800000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ -.byte4 0x03C00000; -.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ -.byte4 0x20000000; -.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ - -#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537)) -.byte4 0xFF800000; -.byte4(L1_DMEMORY); -.byte4 0xFF801000; -.byte4(L1_DMEMORY); -.byte4 0xFF802000; -.byte4(L1_DMEMORY); -.byte4 0xFF803000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFF804000; -.byte4(L1_DMEMORY); -.byte4 0xFF805000; -.byte4(L1_DMEMORY); -.byte4 0xFF806000; -.byte4(L1_DMEMORY); -.byte4 0xFF807000; -.byte4(L1_DMEMORY); -#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537)) -.byte4 0xFF900000; -.byte4(L1_DMEMORY); -.byte4 0xFF901000; -.byte4(L1_DMEMORY); -.byte4 0xFF902000; -.byte4(L1_DMEMORY); -.byte4 0xFF903000; -.byte4(L1_DMEMORY); -#endif -.byte4 0xFF904000; -.byte4(L1_DMEMORY); -.byte4 0xFF905000; -.byte4(L1_DMEMORY); -.byte4 0xFF906000; -.byte4(L1_DMEMORY); -.byte4 0xFF907000; -.byte4(L1_DMEMORY); - -.byte4 0xFFB00000; -.byte4(L1_DMEMORY); - -.byte4 0xffffffff; /*end of section - termination */ - -#ifdef CONFIG_CPLB_INFO -.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ -_ipdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 90 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ - -.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ -_dpdt_swapcount_table: -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 10 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 20 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 30 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 40 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 50 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 60 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 70 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 80 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 100 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 110 */ -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; -.byte4 0x00000000; /* 120 */ - -#endif - -#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/arch-bf537/irq.h b/include/asm-blackfin/arch-bf537/irq.h index 4cb4c1502f..527d8a21f2 100644 --- a/include/asm-blackfin/arch-bf537/irq.h +++ b/include/asm-blackfin/arch-bf537/irq.h @@ -1,7 +1,7 @@ /* * U-boot bf537_irq.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c @@ -33,8 +33,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF537_IRQ_H_ diff --git a/include/asm-blackfin/arch-bf561/bf561_serial.h b/include/asm-blackfin/arch-bf561/bf561_serial.h index 0810228397..eb01ca25ba 100644 --- a/include/asm-blackfin/arch-bf561/bf561_serial.h +++ b/include/asm-blackfin/arch-bf561/bf561_serial.h @@ -1,7 +1,7 @@ /* * U-boot bf561_serial.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF561_SERIAL_H_ diff --git a/include/asm-blackfin/arch-common/bf53x_rtc.h b/include/asm-blackfin/arch-common/bf53x_rtc.h index bc09922a5e..f4440a8d47 100644 --- a/include/asm-blackfin/arch-common/bf53x_rtc.h +++ b/include/asm-blackfin/arch-common/bf53x_rtc.h @@ -1,7 +1,7 @@ /* * U-boot - bf533_rtc.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BF533_RTC_H_ diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index 7766c4ab06..438e50b8e8 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -1,7 +1,7 @@ /* * U-boot - bitops.h Routines for bit operations * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_BITOPS_H diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index 0ec92071b5..bf502a4e62 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -1,7 +1,7 @@ /* * U-boot - blackfin.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_H_ diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h index 2190215971..451d29c3cf 100644 --- a/include/asm-blackfin/blackfin_defs.h +++ b/include/asm-blackfin/blackfin_defs.h @@ -1,7 +1,7 @@ /* * U-boot - blackfin_defs.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_DEFS_H__ diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h index 3b4df4e134..a1a52a5c1a 100644 --- a/include/asm-blackfin/byteorder.h +++ b/include/asm-blackfin/byteorder.h @@ -1,7 +1,7 @@ /* * U-boot - byteorder.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_BYTEORDER_H diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index dd695e10ad..9d8d9ecc87 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -50,7 +50,7 @@ #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ @@ -61,20 +61,20 @@ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) #else /*Write Through */ #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) -#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) #endif #if defined(CONFIG_BF561) -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */ +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ #else -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */ +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ #endif #endif /* _CPLB_H */ diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h index 108c2792a0..ed2b851e95 100644 --- a/include/asm-blackfin/current.h +++ b/include/asm-blackfin/current.h @@ -1,7 +1,7 @@ /* * U-boot - current.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_CURRENT_H diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h index 0c01e9fb7d..ea0b3664e0 100644 --- a/include/asm-blackfin/delay.h +++ b/include/asm-blackfin/delay.h @@ -1,7 +1,7 @@ /* * U-boot - delay.h Routines for introducing delays * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_DELAY_H diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index b64d406992..eb84f11bdb 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -1,7 +1,7 @@ /* * U-boot - entry.h Routines for context saving and restoring * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_ENTRY_H @@ -27,7 +27,6 @@ #include <linux/config.h> #include <asm/setup.h> -#include <asm/page.h> /* * Stack layout in 'ret_from_exception': diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h index 713bba0b22..0d2c618030 100644 --- a/include/asm-blackfin/errno.h +++ b/include/asm-blackfin/errno.h @@ -1,7 +1,7 @@ /* * U-boot - errno.h Error number defines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_ERRNO_H diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 1c738533c8..9024d0a06e 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -1,7 +1,7 @@ /* * U-boot - global_data.h Declarations for global data of u-boot * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __ASM_GBL_DATA_H diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h index baa3e0c5c3..9b360553cb 100644 --- a/include/asm-blackfin/hw_irq.h +++ b/include/asm-blackfin/hw_irq.h @@ -1,7 +1,7 @@ /* * U-boot - hw_irq.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h @@ -24,8 +24,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <linux/config.h> diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h index 3c087c33ee..5d0ad06184 100644 --- a/include/asm-blackfin/io-kernel.h +++ b/include/asm-blackfin/io-kernel.h @@ -1,7 +1,7 @@ /* * U-boot - io-kernel.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_IO_H diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 6bab6e766a..332d2c6437 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -1,7 +1,7 @@ /* * U-boot - io.h IO routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_IO_H @@ -37,6 +37,7 @@ extern void cf_outb(unsigned char val, volatile unsigned char *addr); static inline void sync(void) { + __builtin_bfin_ssync(); } /* diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h index aede742120..1fff316881 100644 --- a/include/asm-blackfin/irq.h +++ b/include/asm-blackfin/irq.h @@ -1,7 +1,7 @@ /* * U-boot - irq.h Interrupt related header file * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file was based on * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c @@ -31,8 +31,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_IRQ_H_ diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h index 18f0c36d24..4fc1acf0ba 100644 --- a/include/asm-blackfin/linkage.h +++ b/include/asm-blackfin/linkage.h @@ -1,7 +1,7 @@ /* * U-boot - linkage.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _LINUX_LINKAGE_H diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h index 4fea74c6c9..8bf94738ec 100644 --- a/include/asm-blackfin/machdep.h +++ b/include/asm-blackfin/machdep.h @@ -1,7 +1,7 @@ /* * U-boot - machdep.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_MACHDEP_H diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index d9d8bf9ba2..cb448ad61e 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -1,7 +1,7 @@ /* * U-boot - mem_init.h Header file for memory initialization * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h deleted file mode 100644 index d59828cdac..0000000000 --- a/include/asm-blackfin/page.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * U-boot - page.h - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _BLACKFIN_PAGE_H -#define _BLACKFIN_PAGE_H - -#include <linux/config.h> - -/* PAGE_SHIFT determines the page size */ - -#define PAGE_SHIFT (12) -#define PAGE_SIZE (4096) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#ifdef __KERNEL__ - -#include <asm/setup.h> - -#if PAGE_SHIFT < 13 -#define KTHREAD_SIZE (8192) -#else -#define KTHREAD_SIZE PAGE_SIZE -#endif - -#ifndef __ASSEMBLY__ - -#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -#define free_user_page(page, addr) free_page(addr) - -#define clear_page(page) memset((page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(page, vaddr) clear_page(page) -#define copy_user_page(to, from, vaddr) copy_page(to, from) - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { - unsigned long pte; -} pte_t; -typedef struct { - unsigned long pmd[16]; -} pmd_t; -typedef struct { - unsigned long pgd; -} pgd_t; -typedef struct { - unsigned long pgprot; -} pgprot_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* to align the pointer to the (next) page boundary */ -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) - -/* Pure 2^n version of get_order */ -extern __inline__ int get_order(unsigned long size) -{ - int order; - - size = (size - 1) >> (PAGE_SHIFT - 1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -#endif /* !__ASSEMBLY__ */ - -#include <asm/page_offset.h> - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - -#define __pa(vaddr) virt_to_phys((void *)vaddr) -#define __va(paddr) phys_to_virt((unsigned long)paddr) - -#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) -#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#define PAGE_BUG(page) do { \ - BUG(); \ -} while (0) - -#endif - -#endif - -#endif diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h index 262473fc3d..cfd8f1fef3 100644 --- a/include/asm-blackfin/page_offset.h +++ b/include/asm-blackfin/page_offset.h @@ -1,7 +1,7 @@ /* * U-boot - page_offset.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index f1f2b5ffc2..27889e8e85 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h @@ -1,7 +1,7 @@ /* * U-boot - posix_types.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __ARCH_BLACKFIN_POSIX_TYPES_H diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index df49bedc0a..6cd4f567fc 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -1,7 +1,7 @@ /* * U-boot - processor.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * include/asm-m68k/processor.h @@ -23,8 +23,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __ASM_BLACKFIN_PROCESSOR_H diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h index afd57773ac..f1b7d0064b 100644 --- a/include/asm-blackfin/ptrace.h +++ b/include/asm-blackfin/ptrace.h @@ -1,7 +1,7 @@ /* * U-boot - ptrace.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_PTRACE_H diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h index 9e6d817fc7..f309543742 100644 --- a/include/asm-blackfin/segment.h +++ b/include/asm-blackfin/segment.h @@ -1,7 +1,7 @@ /* * U-boot - segment.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_SEGMENT_H diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h index a3c1715b4a..b6b82679ec 100644 --- a/include/asm-blackfin/setup.h +++ b/include/asm-blackfin/setup.h @@ -1,7 +1,7 @@ /* * U-boot - setup.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * asm/setup.h -- Definition of the Linux/Blackfin setup information @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_SETUP_H diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h index fbef18618c..d280ffeeaa 100644 --- a/include/asm-blackfin/shared_resources.h +++ b/include/asm-blackfin/shared_resources.h @@ -1,7 +1,7 @@ /* * U-boot - setup.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _SHARED_RESOURCES_H_ diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index aac6bc99f5..dd50207092 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -1,7 +1,7 @@ /* * U-boot - string.h String functions * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* Changed by Lineo Inc. May 2001 */ @@ -30,7 +30,6 @@ #ifdef __KERNEL__ /* only set these up for kernel code */ #include <asm/setup.h> -#include <asm/page.h> #include <config.h> #include <asm/blackfin.h> diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h index 0e53adfe0f..eda887fb62 100644 --- a/include/asm-blackfin/system.h +++ b/include/asm-blackfin/system.h @@ -1,7 +1,7 @@ /* * U-boot - system.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_SYSTEM_H diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index 29e6eba6fa..b90cedacbc 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h @@ -1,7 +1,7 @@ /* * U-boot - traps.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * linux/include/asm/traps.h @@ -23,8 +23,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h index 942ed275af..665a419f2b 100644 --- a/include/asm-blackfin/types.h +++ b/include/asm-blackfin/types.h @@ -1,7 +1,7 @@ /* * U-boot - types.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _BLACKFIN_TYPES_H diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h index e1a435a137..b4928da4f5 100644 --- a/include/asm-blackfin/u-boot.h +++ b/include/asm-blackfin/u-boot.h @@ -1,7 +1,7 @@ /* * U-boot - u-boot.h Structure declarations for board specific data * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,15 +21,15 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 typedef struct bd_info { - int bi_baudrate; /* serial console baudrate */ + int bi_baudrate; /* serial console baudrate */ unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet adress */ unsigned long bi_arch_number; /* unique id for this board */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h index 61e2bfea7c..6e913bb85b 100644 --- a/include/asm-blackfin/uaccess.h +++ b/include/asm-blackfin/uaccess.h @@ -1,7 +1,7 @@ /* * U-boot - uaccess.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * This file is based on * Based on: include/asm-m68knommu/uaccess.h @@ -22,8 +22,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_UACCESS_H diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h index 769f5a089c..9eda9f8554 100644 --- a/include/asm-blackfin/virtconvert.h +++ b/include/asm-blackfin/virtconvert.h @@ -1,7 +1,7 @@ /* * U-boot - virtconvert.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_VIRT_CONVERT__ @@ -33,7 +33,6 @@ #include <linux/config.h> #include <asm/setup.h> -#include <asm/page.h> #define mm_vtop(vaddr) ((unsigned long) vaddr) #define mm_ptov(vaddr) ((unsigned long) vaddr) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index c113b7ee0e..26bc875f86 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -49,6 +49,9 @@ typedef struct global_data { unsigned long scc_clk; unsigned long brg_clk; #endif +#if defined(CONFIG_MPC7448HPC2) + unsigned long mem_clk; +#endif #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 0d3825413e..598811240a 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -182,7 +182,7 @@ #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" /* diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 8da29c4afc..a12c8da13e 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Detlev Zundel, dzu@denx.de + * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -237,18 +237,8 @@ /* * NAND flash support */ -#define CFG_NAND_LEGACY - #define CFG_MAX_NAND_DEVICE 1 -#define NAND_ChipID_UNKNOWN 0x00 -#define SECTORSIZE 512 -#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define ADDR_COLUMN 1 -#define NAND_NO_RB - /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 458ebabeb9..beaf3851dc 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -62,11 +62,14 @@ */ #define CFG_PLL0_OPT 0x04 -#define CFG_USART1 1 - -#define CFG_CONSOLE_UART_DEV DEVICE_USART1 +#undef CONFIG_USART0 +#define CONFIG_USART1 1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 /* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMDLINE_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 @@ -75,16 +78,47 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" + "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * These are "locally administered ethernet addresses" generated by + * ./tools/gen_eth_addr + * + * After booting the board for the first time, new addresses should be + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ + | CONFIG_BOOTP_GATEWAY) #define CONFIG_COMMANDS (CFG_CMD_BDI \ | CFG_CMD_LOADS \ | CFG_CMD_LOADB \ - /* | CFG_CMD_IMI */ \ + | CFG_CMD_IMI \ /* | CFG_CMD_CACHE */ \ | CFG_CMD_FLASH \ | CFG_CMD_MEMORY \ - /* | CFG_CMD_NET */ \ + | CFG_CMD_NET \ | CFG_CMD_ENV \ /* | CFG_CMD_IRQ */ \ | CFG_CMD_BOOTD \ @@ -96,7 +130,7 @@ /* | CFG_CMD_I2C */ \ | CFG_CMD_REGINFO \ /* | CFG_CMD_DATE */ \ - /* | CFG_CMD_DHCP */ \ + | CFG_CMD_DHCP \ /* | CFG_CMD_AUTOSCRIPT */ \ /* | CFG_CMD_MII */ \ | CFG_CMD_MISC \ @@ -106,19 +140,22 @@ /* | CFG_CMD_SAVES */ \ /* | CFG_CMD_SPI */ \ /* | CFG_CMD_PING */ \ - /* | CFG_CMD_MMC */ \ - /* | CFG_CMD_FAT */ \ - /* | CFG_CMD_IMLS */ \ + | CFG_CMD_MMC \ + | CFG_CMD_FAT \ + | CFG_CMD_IMLS \ /* | CFG_CMD_ITEST */ \ - /* | CFG_CMD_EXT2 */ \ + | CFG_CMD_EXT2 \ + | CFG_CMD_JFFS2 \ ) #include <cmd_confdefs.h> #define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 #define CONFIG_PIO2 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 @@ -150,16 +187,8 @@ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) #define CFG_MALLOC_LEN (256*1024) -#define CFG_MALLOC_END \ - ({ \ - DECLARE_GLOBAL_DATA_PTR; \ - CFG_SDRAM_BASE + gd->sdram_size; \ - }) -#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) - #define CFG_DMA_ALLOC_LEN (16384) -#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) -#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) #define CFG_BOOTPARAMS_LEN (16 * 1024) diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h new file mode 100644 index 0000000000..243a3f6c8f --- /dev/null +++ b/include/configs/mpc7448hpc2.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * + * (C) Copyright 2006 + * Alex Bounine , Tundra Semiconductor Corp. + * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board specific configuration options for Freescale + * MPC7448HPC2 (High-Performance Computing II) (Taiga) board + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* Board Configuration Definitions */ +/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */ + +#define CONFIG_MPC7448HPC2 + +#define CONFIG_74xx +#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_ALTIVEC /* undef to disable */ + +#define CFG_BOARD_NAME "MPC7448 HPC II" +#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II" + +#define CFG_OCN_CLK 133000000 /* 133 MHz */ +#define CFG_CONFIG_BUS_CLK 133000000 + +#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */ + +#undef CONFIG_ECC /* disable ECC support */ + +/* Board-specific Initialization Functions to be called */ +#define CFG_BOARD_ASM_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HAS_ETH1 + +#define CONFIG_ENV_OVERWRITE + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ + +/*#define CFG_HUSH_PARSER */ +#undef CFG_HUSH_PARSER + +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,7448@0" +#define OF_TSI "tsi108@c0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" + +/* + * The following defines let you select what serial you want to use + * for your console driver. + * + * what to do: + * If you have hacked a serial cable onto the second DUART channel, + * change the CFG_DUART port from 1 to 0 below. + * + */ + +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK CFG_OCN_CLK * 8 + +#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808) +#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08) +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#undef CONFIG_BOOTARGS +/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" + * to mount root filesystem over NFS;echo" */ + +#if (CONFIG_BOOTDELAY >= 0) +#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\ + setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \ + ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; " + +#define CONFIG_BOOTARGS "console=ttyS0,115200" +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS + +#define CONFIG_SERIAL "No. 1" + +/* Networking Configuration */ + +#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ + +#define CONFIG_TSI108_ETH +#define CONFIG_TSI108_ETH_NUM_PORTS 2 + +#define CONFIG_NET_MULTI + +#define CONFIG_BOOTFILE zImage.initrd.elf +#define CONFIG_LOADADDR 0x400000 + +/*-------------------------------------------------------------------------- */ + +#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_CACHE \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_SDRAM \ + | CFG_CMD_EEPROM \ + | CFG_CMD_FLASH \ + | CFG_CMD_ENV \ + | CFG_CMD_BSP \ + | CFG_CMD_DHCP \ + | CFG_CMD_PING \ + | CFG_CMD_DATE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*set date in u-boot*/ +#define CONFIG_RTC_M48T35A +#define CFG_NVRAM_BASE_ADDR 0xfc000000 +#define CFG_NVRAM_SIZE 0x8000 +/* + * Miscellaneous configurable options + */ +#define CONFIG_VERSION_VARIABLE 1 +#define CONFIG_TSI108_I2C + +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ + +#define CFG_HZ 1000 /* decr freq: 1ms ticks */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + +/* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized + */ +#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */ +#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */ + +#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ + +#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */ +#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */ + +#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */ +#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */ + +#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */ + +#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */ + +#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */ + +#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */ +#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */ + +#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */ + +#define PCI0_IO_BASE_BOOTM 0xfd000000 + +#define CFG_RESET_ADDRESS 0x3fffff00 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ + +/* Peripheral Device section */ + +/* + * Resources on the Tsi108 + */ + +#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */ +#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */ + +#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */ + +#undef DISABLE_PBM + +/* + * PCI stuff + * + */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_TSI108_PCI /* include tsi108 pci support */ + +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +/* PCI MEMORY MAP section */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* PCI Memory Space */ +#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) +#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */ +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */ + +/* PCI I/O Space */ +#define CFG_PCI_IO_BUS 0x00000000 +#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */ + +#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */ + +#define _IO_BASE 0x00000000 /* points to PCI I/O space */ + +/* PCI Config Space mapping */ +#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ +#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */ + +#define CFG_IBAT0U 0xFE0003FF +#define CFG_IBAT0L 0xFE000002 + +#define CFG_IBAT1U 0x00007FFF +#define CFG_IBAT1L 0x00000012 + +#define CFG_IBAT2U 0x80007FFF +#define CFG_IBAT2L 0x80000022 + +#define CFG_IBAT3U 0x00000000 +#define CFG_IBAT3L 0x00000000 + +#define CFG_IBAT4U 0x00000000 +#define CFG_IBAT4L 0x00000000 + +#define CFG_IBAT5U 0x00000000 +#define CFG_IBAT5L 0x00000000 + +#define CFG_IBAT6U 0x00000000 +#define CFG_IBAT6L 0x00000000 + +#define CFG_IBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 + +#define CFG_DBAT0U 0xE0003FFF +#define CFG_DBAT0L 0xE000002A + +#define CFG_DBAT1U 0x00007FFF +#define CFG_DBAT1L 0x00000012 + +#define CFG_DBAT2U 0x00000000 +#define CFG_DBAT2L 0x00000000 + +#define CFG_DBAT3U 0xC0000003 +#define CFG_DBAT3L 0xC000002A + +#define CFG_DBAT4U 0x00000000 +#define CFG_DBAT4L 0x00000000 + +#define CFG_DBAT5U 0x00000000 +#define CFG_DBAT5L 0x00000000 + +#define CFG_DBAT6U 0x00000000 +#define CFG_DBAT6L 0x00000000 + +#define CFG_DBAT7U 0x00000000 +#define CFG_DBAT7L 0x00000000 + +/* I2C addresses for the two DIMM SPD chips */ +#define DIMM0_I2C_ADDR 0x51 +#define DIMM1_I2C_ADDR 0x52 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_WRITE_SWAPPED_DATA + +#define PHYS_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_SECT (128) + +#define CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_ADDR 0xFC000000 + +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ +#undef CFG_L2 + +#define L2_INIT 0 +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_SERIAL_HANG_IN_EXCEPTION +#endif /* __CONFIG_H */ diff --git a/include/fdt.h b/include/fdt.h index 48ccfd9100..3dd3aca3b6 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -1,3 +1,22 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef _FDT_H #define _FDT_H diff --git a/include/fdt_support.h b/include/fdt_support.h new file mode 100644 index 0000000000..a276834740 --- /dev/null +++ b/include/fdt_support.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2007 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FDT_SUPPORT_H +#define __FDT_SUPPORT_H + +#ifdef CONFIG_OF_LIBFDT + +#include <fdt.h> + +int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force); + +#ifdef CONFIG_OF_HAS_UBOOT_ENV +int fdt_env(void *fdt); +#endif + +#ifdef CONFIG_OF_HAS_BD_T +int fdt_bd_t(void *fdt); +#endif + +#endif /* ifdef CONFIG_OF_LIBFDT */ +#endif /* ifndef __FDT_SUPPORT_H */ diff --git a/include/libfdt.h b/include/libfdt.h index a0b4d55034..f8bac73a31 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1,5 +1,3 @@ -#ifndef _LIBFDT_H -#define _LIBFDT_H /* * libfdt - Flat Device Tree manipulation * Copyright (C) 2006 David Gibson, IBM Corporation. @@ -19,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef _LIBFDT_H +#define _LIBFDT_H + #include <fdt.h> #include <libfdt_env.h> @@ -60,6 +61,8 @@ #define fdt_set_header(fdt, field, val) \ ((struct fdt_header *)(fdt))->field = cpu_to_fdt32(val) +int fdt_check_header(const void *fdt); + void *fdt_offset_ptr(const void *fdt, int offset, int checklen); #define fdt_offset_ptr_typed(fdt, offset, var) \ @@ -83,6 +86,8 @@ void *fdt_getprop(const void *fdt, int nodeoffset, uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset, char **namep); +int fdt_num_reservemap(void *fdt, int *used, int *total); +int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re); /* Write-in-place functions */ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, @@ -96,6 +101,8 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, int fdt_nop_property(void *fdt, int nodeoffset, const char *name); int fdt_nop_node(void *fdt, int nodeoffset); +int fdt_insert_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size); + /* Sequential-write functions */ int fdt_create(void *buf, int bufsize); @@ -112,6 +119,7 @@ int fdt_property(void *fdt, const char *name, const void *val, int len); fdt_property(fdt, name, str, strlen(str)+1) int fdt_end_node(void *fdt); int fdt_finish(void *fdt); +int fdt_replace_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size); /* Read-write functions */ int fdt_open_into(void *fdt, void *buf, int bufsize); diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 6c77852540..e746314b1e 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -1,3 +1,23 @@ +/* + * libfdt - Flat Device Tree manipulation (build/run environment adaptation) + * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com + * Original version written by David Gibson, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public License + * as published by the Free Software Foundation; either version 2.1 of + * the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef _LIBFDT_ENV_H #define _LIBFDT_ENV_H diff --git a/include/linux/mii.h b/include/linux/mii.h new file mode 100644 index 0000000000..7c63095fd4 --- /dev/null +++ b/include/linux/mii.h @@ -0,0 +1,158 @@ +/* + * linux/mii.h: definitions for MII-compatible transceivers + * Originally drivers/net/sunhme.h. + * + * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com) + */ + +#ifndef __LINUX_MII_H__ +#define __LINUX_MII_H__ + +/* Generic MII registers. */ + +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x07c0 /* Unused... */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Link partner ability register. */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_RESV 0x1c00 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* Expansion register for auto-negotiation. */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +/* N-way test register. */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + + +/** + * mii_nway_result + * @negotiated: value of MII ANAR and'd with ANLPAR + * + * Given a set of MII abilities, check each bit and returns the + * currently supported media, in the priority order defined by + * IEEE 802.3u. We use LPA_xxx constants but note this is not the + * value of LPA solely, as described above. + * + * The one exception to IEEE 802.3u is that 100baseT4 is placed + * between 100T-full and 100T-half. If your phy does not support + * 100T4 this is fine. If your phy places 100T4 elsewhere in the + * priority order, you will need to roll your own function. + */ +static inline unsigned int mii_nway_result (unsigned int negotiated) +{ + unsigned int ret; + + if (negotiated & LPA_100FULL) + ret = LPA_100FULL; + else if (negotiated & LPA_100BASE4) + ret = LPA_100BASE4; + else if (negotiated & LPA_100HALF) + ret = LPA_100HALF; + else if (negotiated & LPA_10FULL) + ret = LPA_10FULL; + else + ret = LPA_10HALF; + + return ret; +} + +/** + * mii_duplex + * @duplex_lock: Non-zero if duplex is locked at full + * @negotiated: value of MII ANAR and'd with ANLPAR + * + * A small helper function for a common case. Returns one + * if the media is operating or locked at full duplex, and + * returns zero otherwise. + */ +static inline unsigned int mii_duplex (unsigned int duplex_lock, + unsigned int negotiated) +{ + if (duplex_lock) + return 1; + if (mii_nway_result(negotiated) & LPA_DUPLEX) + return 1; + return 0; +} + + +#endif /* __LINUX_MII_H__ */ diff --git a/include/linux/stat.h b/include/linux/stat.h index 4d05aa92d9..43fd53fc98 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -7,7 +7,7 @@ extern "C" { #endif -#define S_IFMT 00170000 /* type of file */ +#define S_IFMT 00170000 /* type of file */ #define S_IFSOCK 0140000 /* named socket */ #define S_IFLNK 0120000 /* symbolic link */ #define S_IFREG 0100000 /* regular */ @@ -49,20 +49,20 @@ struct stat { ino_t st_ino; /* file id */ mode_t st_mode; /* ownership/protection */ nlink_t st_nlink; /* number of links */ - uid_t st_uid; /* user id */ - gid_t st_gid; /* group id */ + uid_t st_uid; /* user id */ + gid_t st_gid; /* group id */ dev_t st_rdev; off_t st_size; /* file size in # of bytes */ - unsigned long st_blksize; /* block size */ - unsigned long st_blocks; /* file size in # of blocks */ - unsigned long st_atime; /* time file was last accessed */ - unsigned long __unused1; - unsigned long st_mtime; /* time file was last modified */ - unsigned long __unused2; - unsigned long st_ctime; /* time file status was last changed */ - unsigned long __unused3; - unsigned long __unused4; - unsigned long __unused5; + unsigned long st_blksize; /* block size */ + unsigned long st_blocks; /* file size in # of blocks */ + unsigned long st_atime; /* time file was last accessed */ + unsigned long __unused1; + unsigned long st_mtime; /* time file was last modified */ + unsigned long __unused2; + unsigned long st_ctime; /* time file status was last changed */ + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; }; #endif /* __PPC__ */ @@ -97,34 +97,59 @@ struct stat { #if defined (__MIPS__) struct stat { - dev_t st_dev; - long st_pad1[3]; - ino_t st_ino; - mode_t st_mode; - nlink_t st_nlink; - uid_t st_uid; - gid_t st_gid; - dev_t st_rdev; - long st_pad2[2]; - off_t st_size; - long st_pad3; + dev_t st_dev; + long st_pad1[3]; + ino_t st_ino; + mode_t st_mode; + nlink_t st_nlink; + uid_t st_uid; + gid_t st_gid; + dev_t st_rdev; + long st_pad2[2]; + off_t st_size; + long st_pad3; /* * Actually this should be timestruc_t st_atime, st_mtime and st_ctime * but we don't have it under Linux. */ - time_t st_atime; - long reserved0; - time_t st_mtime; - long reserved1; - time_t st_ctime; - long reserved2; - long st_blksize; - long st_blocks; - long st_pad4[14]; + time_t st_atime; + long reserved0; + time_t st_mtime; + long reserved1; + time_t st_ctime; + long reserved2; + long st_blksize; + long st_blocks; + long st_pad4[14]; }; #endif /* __MIPS__ */ +#if defined(__AVR32__) + +struct stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __AVR32__ */ + #ifdef __cplusplus } #endif diff --git a/include/tsi108.h b/include/tsi108.h new file mode 100644 index 0000000000..ba62e7abe6 --- /dev/null +++ b/include/tsi108.h @@ -0,0 +1,221 @@ +/***************************************************************************** + * (C) Copyright 2003; Tundra Semiconductor Corp. + * (C) Copyright 2006; Freescale Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + *****************************************************************************/ + +/* + * FILENAME: tsi108.h + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Common definitions for the Tundra Tsi108 bridge chip + * + */ + +#ifndef _TSI108_H_ +#define _TSI108_H_ + +#define TSI108_HLP_REG_OFFSET (0x0000) +#define TSI108_PCI_REG_OFFSET (0x1000) +#define TSI108_CLK_REG_OFFSET (0x2000) +#define TSI108_PB_REG_OFFSET (0x3000) +#define TSI108_SD_REG_OFFSET (0x4000) +#define TSI108_MPIC_REG_OFFSET (0x7400) + +#define PB_ID (0x000) +#define PB_RSR (0x004) +#define PB_BUS_MS_SELECT (0x008) +#define PB_ISR (0x00C) +#define PB_ARB_CTRL (0x018) +#define PB_PVT_CTRL2 (0x034) +#define PB_SCR (0x400) +#define PB_ERRCS (0x404) +#define PB_AERR (0x408) +#define PB_REG_BAR (0x410) +#define PB_OCN_BAR1 (0x414) +#define PB_OCN_BAR2 (0x418) +#define PB_SDRAM_BAR1 (0x41C) +#define PB_SDRAM_BAR2 (0x420) +#define PB_MCR (0xC00) +#define PB_MCMD (0xC04) + +#define HLP_B0_ADDR (0x000) +#define HLP_B1_ADDR (0x010) +#define HLP_B2_ADDR (0x020) +#define HLP_B3_ADDR (0x030) + +#define HLP_B0_MASK (0x004) +#define HLP_B1_MASK (0x014) +#define HLP_B2_MASK (0x024) +#define HLP_B3_MASK (0x034) + +#define HLP_B0_CTRL0 (0x008) +#define HLP_B1_CTRL0 (0x018) +#define HLP_B2_CTRL0 (0x028) +#define HLP_B3_CTRL0 (0x038) + +#define HLP_B0_CTRL1 (0x00C) +#define HLP_B1_CTRL1 (0x01C) +#define HLP_B2_CTRL1 (0x02C) +#define HLP_B3_CTRL1 (0x03C) + +#define PCI_CSR (0x004) +#define PCI_P2O_BAR0 (0x010) +#define PCI_P2O_BAR0_UPPER (0x014) +#define PCI_P2O_BAR2 (0x018) +#define PCI_P2O_BAR2_UPPER (0x01C) +#define PCI_P2O_BAR3 (0x020) +#define PCI_P2O_BAR3_UPPER (0x024) + +#define PCI_MISC_CSR (0x040) +#define PCI_P2O_PAGE_SIZES (0x04C) + +#define PCI_PCIX_STAT (0x0F4) + +#define PCI_IRP_STAT (0x184) + +#define PCI_PFAB_BAR0 (0x204) +#define PCI_PFAB_BAR0_UPPER (0x208) +#define PCI_PFAB_IO (0x20C) +#define PCI_PFAB_IO_UPPER (0x210) + +#define PCI_PFAB_MEM32 (0x214) +#define PCI_PFAB_MEM32_REMAP (0x218) +#define PCI_PFAB_MEM32_MASK (0x21C) + +#define CG_PLL0_CTRL0 (0x210) +#define CG_PLL0_CTRL1 (0x214) +#define CG_PLL1_CTRL0 (0x220) +#define CG_PLL1_CTRL1 (0x224) +#define CG_PWRUP_STATUS (0x234) + +#define MPIC_CSR(n) (0x30C + (n * 0x40)) + +#define SD_CTRL (0x000) +#define SD_STATUS (0x004) +#define SD_TIMING (0x008) +#define SD_REFRESH (0x00C) +#define SD_INT_STATUS (0x010) +#define SD_INT_ENABLE (0x014) +#define SD_INT_SET (0x018) +#define SD_D0_CTRL (0x020) +#define SD_D1_CTRL (0x024) +#define SD_D0_BAR (0x028) +#define SD_D1_BAR (0x02C) +#define SD_ECC_CTRL (0x040) +#define SD_DLL_STATUS (0x250) + +#define TS_SD_CTRL_ENABLE (1 << 31) + +#define PB_ERRCS_ES (1 << 1) +#define PB_ISR_PBS_RD_ERR (1 << 8) +#define PCI_IRP_STAT_P_CSR (1 << 23) + +/* + * I2C : Register address offset definitions + */ +#define I2C_CNTRL1 (0x00000000) +#define I2C_CNTRL2 (0x00000004) +#define I2C_RD_DATA (0x00000008) +#define I2C_TX_DATA (0x0000000c) + +/* + * I2C : Register Bit Masks and Reset Values + * definitions for every register + */ + +/* I2C_CNTRL1 : Reset Value */ +#define I2C_CNTRL1_RESET_VALUE (0x0000000a) + +/* I2C_CNTRL1 : Register Bits Masks Definitions */ +#define I2C_CNTRL1_DEVCODE (0x0000000f) +#define I2C_CNTRL1_PAGE (0x00000700) +#define I2C_CNTRL1_BYTADDR (0x00ff0000) +#define I2C_CNTRL1_I2CWRITE (0x01000000) + +/* I2C_CNTRL1 : Read/Write Bit Mask Definition */ +#define I2C_CNTRL1_RWMASK (0x01ff070f) + +/* I2C_CNTRL1 : Unused/Reserved bits Definition */ +#define I2C_CNTRL1_RESERVED (0xfe00f8f0) + +/* I2C_CNTRL2 : Reset Value */ +#define I2C_CNTRL2_RESET_VALUE (0x00000000) + +/* I2C_CNTRL2 : Register Bits Masks Definitions */ +#define I2C_CNTRL2_SIZE (0x00000003) +#define I2C_CNTRL2_LANE (0x0000000c) +#define I2C_CNTRL2_MULTIBYTE (0x00000010) +#define I2C_CNTRL2_START (0x00000100) +#define I2C_CNTRL2_WR_STATUS (0x00010000) +#define I2C_CNTRL2_RD_STATUS (0x00020000) +#define I2C_CNTRL2_I2C_TO_ERR (0x04000000) +#define I2C_CNTRL2_I2C_CFGERR (0x08000000) +#define I2C_CNTRL2_I2C_CMPLT (0x10000000) + +/* I2C_CNTRL2 : Read/Write Bit Mask Definition */ +#define I2C_CNTRL2_RWMASK (0x0000011f) + +/* I2C_CNTRL2 : Unused/Reserved bits Definition */ +#define I2C_CNTRL2_RESERVED (0xe3fcfee0) + +/* I2C_RD_DATA : Reset Value */ +#define I2C_RD_DATA_RESET_VALUE (0x00000000) + +/* I2C_RD_DATA : Register Bits Masks Definitions */ +#define I2C_RD_DATA_RBYTE0 (0x000000ff) +#define I2C_RD_DATA_RBYTE1 (0x0000ff00) +#define I2C_RD_DATA_RBYTE2 (0x00ff0000) +#define I2C_RD_DATA_RBYTE3 (0xff000000) + +/* I2C_RD_DATA : Read/Write Bit Mask Definition */ +#define I2C_RD_DATA_RWMASK (0x00000000) + +/* I2C_RD_DATA : Unused/Reserved bits Definition */ +#define I2C_RD_DATA_RESERVED (0x00000000) + +/* I2C_TX_DATA : Reset Value */ +#define I2C_TX_DATA_RESET_VALUE (0x00000000) + +/* I2C_TX_DATA : Register Bits Masks Definitions */ +#define I2C_TX_DATA_TBYTE0 (0x000000ff) +#define I2C_TX_DATA_TBYTE1 (0x0000ff00) +#define I2C_TX_DATA_TBYTE2 (0x00ff0000) +#define I2C_TX_DATA_TBYTE3 (0xff000000) + +/* I2C_TX_DATA : Read/Write Bit Mask Definition */ +#define I2C_TX_DATA_RWMASK (0xffffffff) + +/* I2C_TX_DATA : Unused/Reserved bits Definition */ +#define I2C_TX_DATA_RESERVED (0x00000000) + +#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */ +#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */ + +#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */ + +/* I2C status codes */ + +#define TSI108_I2C_SUCCESS 0 +#define TSI108_I2C_PARAM_ERR 1 +#define TSI108_I2C_TIMEOUT_ERR 2 +#define TSI108_I2C_IF_BUSY 3 +#define TSI108_I2C_IF_ERROR 4 + +#endif /* _TSI108_H_ */ diff --git a/lib_avr32/avr32_linux.c b/lib_avr32/avr32_linux.c index d128dfb53f..6095e2ff21 100644 --- a/lib_avr32/avr32_linux.c +++ b/lib_avr32/avr32_linux.c @@ -27,7 +27,7 @@ #include <asm/addrspace.h> #include <asm/io.h> #include <asm/setup.h> -#include <asm/arch/platform.h> +#include <asm/arch/clk.h> DECLARE_GLOBAL_DATA_PTR; @@ -133,7 +133,7 @@ static struct tag *setup_clock_tags(struct tag *params) params->hdr.size = tag_size(tag_clock); params->u.clock.clock_id = ACLOCK_HSB; params->u.clock.clock_flags = 0; - params->u.clock.clock_hz = pm_get_clock_freq(CLOCK_HSB); + params->u.clock.clock_hz = get_hsb_clk_rate(); #endif return tag_next(params); diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 02c106b80e..265328aa48 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -47,11 +47,14 @@ static unsigned long mem_malloc_start = 0; static unsigned long mem_malloc_end = 0; static unsigned long mem_malloc_brk = 0; -/* The malloc area is wherever the board wants it to be */ +/* The malloc area is right below the monitor image in RAM */ static void mem_malloc_init(void) { - mem_malloc_start = CFG_MALLOC_START; - mem_malloc_end = CFG_MALLOC_END; + unsigned long monitor_addr; + + monitor_addr = CFG_MONITOR_BASE + gd->reloc_off; + mem_malloc_end = monitor_addr; + mem_malloc_start = mem_malloc_end - CFG_MALLOC_LEN; mem_malloc_brk = mem_malloc_start; printf("malloc: Using memory from 0x%08lx to 0x%08lx\n", @@ -73,6 +76,50 @@ void *sbrk(ptrdiff_t increment) return ((void *)old); } +#ifdef CFG_DMA_ALLOC_LEN +#include <asm/cacheflush.h> +#include <asm/io.h> + +static unsigned long dma_alloc_start; +static unsigned long dma_alloc_end; +static unsigned long dma_alloc_brk; + +static void dma_alloc_init(void) +{ + unsigned long monitor_addr; + + monitor_addr = CFG_MONITOR_BASE + gd->reloc_off; + dma_alloc_end = monitor_addr - CFG_MALLOC_LEN; + dma_alloc_start = dma_alloc_end - CFG_DMA_ALLOC_LEN; + dma_alloc_brk = dma_alloc_start; + + printf("DMA: Using memory from 0x%08lx to 0x%08lx\n", + dma_alloc_start, dma_alloc_end); + + dcache_invalidate_range(cached(dma_alloc_start), + dma_alloc_end - dma_alloc_start); +} + +void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + unsigned long paddr = dma_alloc_brk; + + if (dma_alloc_brk + len > dma_alloc_end) + return NULL; + + dma_alloc_brk = ((paddr + len + CFG_DCACHE_LINESZ - 1) + & ~(CFG_DCACHE_LINESZ - 1)); + + *handle = paddr; + return uncached(paddr); +} +#else +static inline void dma_alloc_init(void) +{ + +} +#endif + static int init_baudrate(void) { char tmp[64]; @@ -122,40 +169,152 @@ static void display_flash_config (void) printf("at address 0x%08lx\n", gd->bd->bi_flashstart); } -void start_u_boot (void) +void board_init_f(ulong board_type) { gd_t gd_data; + gd_t *new_gd; + bd_t *bd; + unsigned long *new_sp; + unsigned long monitor_len; + unsigned long monitor_addr; + unsigned long addr; + long sdram_size; /* Initialize the global data pointer */ memset(&gd_data, 0, sizeof(gd_data)); gd = &gd_data; - monitor_flash_len = _edata - _text; - /* Perform initialization sequence */ + board_early_init_f(); cpu_init(); - timer_init(); env_init(); init_baudrate(); serial_init(); console_init_f(); display_banner(); + sdram_size = initdram(board_type); + + /* If we have no SDRAM, we can't go on */ + if (sdram_size <= 0) + panic("No working SDRAM available\n"); + + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + * + * Reserve memory at end of RAM for (top down in that order): + * - u-boot image + * - heap for malloc() + * - board info struct + * - global data struct + * - stack + */ + addr = CFG_SDRAM_BASE + sdram_size; + monitor_len = _end - _text; + + /* + * Reserve memory for u-boot code, data and bss. + * Round down to next 4 kB limit. + */ + addr -= monitor_len; + addr &= ~(4096UL - 1); + monitor_addr = addr; + + /* Reserve memory for malloc() */ + addr -= CFG_MALLOC_LEN; + +#ifdef CFG_DMA_ALLOC_LEN + /* Reserve DMA memory (must be cache aligned) */ + addr &= ~(CFG_DCACHE_LINESZ - 1); + addr -= CFG_DMA_ALLOC_LEN; +#endif - board_init_memories(); - mem_malloc_init(); + /* Allocate a Board Info struct on a word boundary */ + addr -= sizeof(bd_t); + addr &= ~3UL; + gd->bd = bd = (bd_t *)addr; + + /* Allocate a new global data copy on a 8-byte boundary. */ + addr -= sizeof(gd_t); + addr &= ~7UL; + new_gd = (gd_t *)addr; + + /* And finally, a new, bigger stack. */ + new_sp = (unsigned long *)addr; + gd->stack_end = addr; + *(--new_sp) = 0; + *(--new_sp) = 0; + + /* + * Initialize the board information struct with the + * information we have. + */ + bd->bi_dram[0].start = CFG_SDRAM_BASE; + bd->bi_dram[0].size = sdram_size; + bd->bi_baudrate = gd->baudrate; + + memcpy(new_gd, gd, sizeof(gd_t)); + + relocate_code((unsigned long)new_sp, new_gd, monitor_addr); +} - gd->bd = malloc(sizeof(bd_t)); - memset(gd->bd, 0, sizeof(bd_t)); - gd->bd->bi_baudrate = gd->baudrate; - gd->bd->bi_dram[0].start = CFG_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->sdram_size; +void board_init_r(gd_t *new_gd, ulong dest_addr) +{ + extern void malloc_bin_reloc (void); +#ifndef CFG_ENV_IS_NOWHERE + extern char * env_name_spec; +#endif + cmd_tbl_t *cmdtp; + bd_t *bd; + + gd = new_gd; + bd = gd->bd; + + gd->flags |= GD_FLG_RELOC; + gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + + monitor_flash_len = _edata - _text; + /* + * We have to relocate the command table manually + */ + for (cmdtp = &__u_boot_cmd_start; + cmdtp != &__u_boot_cmd_end; cmdtp++) { + unsigned long addr; + + addr = (unsigned long)cmdtp->cmd + gd->reloc_off; + cmdtp->cmd = (typeof(cmdtp->cmd))addr; + + addr = (unsigned long)cmdtp->name + gd->reloc_off; + cmdtp->name = (typeof(cmdtp->name))addr; + + if (cmdtp->usage) { + addr = (unsigned long)cmdtp->usage + gd->reloc_off; + cmdtp->usage = (typeof(cmdtp->usage))addr; + } +#ifdef CFG_LONGHELP + if (cmdtp->help) { + addr = (unsigned long)cmdtp->help + gd->reloc_off; + cmdtp->help = (typeof(cmdtp->help))addr; + } +#endif + } + + /* there are some other pointer constants we must deal with */ +#ifndef CFG_ENV_IS_NOWHERE + env_name_spec += gd->reloc_off; +#endif + + timer_init(); + mem_malloc_init(); + malloc_bin_reloc(); + dma_alloc_init(); board_init_info(); flash_init(); - if (gd->bd->bi_flashsize) + if (bd->bi_flashsize) display_flash_config(); - if (gd->bd->bi_dram[0].size) + if (bd->bi_dram[0].size) display_dram_config(); gd->bd->bi_boot_params = malloc(CFG_BOOTPARAMS_LEN); @@ -169,6 +328,13 @@ void start_u_boot (void) jumptable_init(); console_init_r(); +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts("Net: "); +#endif + eth_initialize(gd->bd); +#endif + for (;;) { main_loop(); } diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile index 3197fe1c90..a7aaef7a3c 100644 --- a/lib_blackfin/Makefile +++ b/lib_blackfin/Makefile @@ -1,7 +1,7 @@ # # U-boot Makefile # -# Copyright (c) 2005 blackfin.uclinux.org +# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA # include $(TOPDIR)/config.mk diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c index 1b0d90ae67..3b9c4df988 100644 --- a/lib_blackfin/bf533_linux.c +++ b/lib_blackfin/bf533_linux.c @@ -1,7 +1,7 @@ /* * U-boot - bf533_linux.c * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* Dummy functions, currently not in Use */ diff --git a/lib_blackfin/bf533_string.c b/lib_blackfin/bf533_string.c index 85b115076a..1553f1b5ac 100644 --- a/lib_blackfin/bf533_string.c +++ b/lib_blackfin/bf533_string.c @@ -1,7 +1,7 @@ /* * U-boot - bf533_string.c Contains library routines. * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,22 +21,16 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> #include <asm/setup.h> -#include <asm/page.h> #include <config.h> #include <asm/blackfin.h> #include <asm/io.h> - -extern void blackfin_icache_flush_range(const void *, const void *); -extern void blackfin_dcache_flush_range(const void *, const void *); -extern void *memcpy_ASM(void *dest, const void *src, size_t count); - -void *dma_memcpy(void *, const void *, size_t); +#include "cache.h" char *strcpy(char *dest, const char *src) { @@ -118,44 +112,7 @@ int strncmp(const char *cs, const char *ct, size_t count) return __res1; } -/* - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *memcpy(void *dest, const void *src, size_t count) -{ - char *tmp = (char *)dest, *s = (char *)src; - - /* L1_ISRAM can only be accessed via dma */ - if ((tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)) { - /* L1 is the destination */ - dma_memcpy(dest, src, count); - - if (icache_status()) { - blackfin_icache_flush_range(src, src + count); - } - } else if ((s >= (char *)L1_ISRAM) && (s < (char *)L1_ISRAM_END)) { - /* L1 is the source */ - dma_memcpy(dest, src, count); - - if (icache_status()) { - blackfin_icache_flush_range(dest, dest + count); - } - if (dcache_status()) { - blackfin_dcache_flush_range(dest, dest + count); - } - } else { - memcpy_ASM(dest, src, count); - } - return dest; -} - -void *dma_memcpy(void *dest, const void *src, size_t count) +static void *dma_memcpy(void *dest, const void *src, size_t count) { *pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR; @@ -189,3 +146,40 @@ void *dma_memcpy(void *dest, const void *src, size_t count) src += count; return dest; } + +/* + * memcpy - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +extern void *memcpy_ASM(void *dest, const void *src, size_t count); +void *memcpy(void *dest, const void *src, size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + if (dcache_status()) { + blackfin_dcache_flush_range(src, src+count); + } + /* L1_ISRAM can only be accessed via dma */ + if ((tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)) { + /* L1 is the destination */ + dma_memcpy(dest,src,count); + } else if ((s >= (char *)L1_ISRAM) && (s < (char *)L1_ISRAM_END)) { + /* L1 is the source */ + dma_memcpy(dest,src,count); + + if (icache_status()) { + blackfin_icache_flush_range(dest, dest+count); + } + if (dcache_status()) { + blackfin_dcache_invalidate_range(dest, dest+count); + } + } else { + memcpy_ASM(dest,src,count); + } + return dest; +} diff --git a/lib_blackfin/blackfin_board.h b/lib_blackfin/blackfin_board.h index e0b96da875..1353421c33 100644 --- a/lib_blackfin/blackfin_board.h +++ b/lib_blackfin/blackfin_board.h @@ -1,7 +1,7 @@ /* * U-boot - blackfin_board.h * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #ifndef __BLACKFIN_BOARD_H__ diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 1a0a2826c0..1538da3f29 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -1,7 +1,7 @@ /* * U-boot - board.c First C file to be called contains init routines * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #include <common.h> @@ -182,7 +182,7 @@ void init_cplbtables(void) icplb_table[j][1] = L1_IMEMORY; j++; - for (i = 0; i <= CONFIG_MEM_SIZE / 4; i++) { + for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) { icplb_table[j][0] = (i * 4 * 1024 * 1024); if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) { @@ -193,14 +193,19 @@ void init_cplbtables(void) j++; } #if defined(CONFIG_BF561) + /* MAC space */ + icplb_table[j][0] = 0x2C000000; + icplb_table[j][1] = SDRAM_INON_CHBL; + j++; /* Async Memory space */ for (i = 0; i < 3; i++) { - icplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024; - icplb_table[j++][1] = SDRAM_IGENERIC; + icplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024; + icplb_table[j][1] = SDRAM_INON_CHBL; + j++; } #else icplb_table[j][0] = 0x20000000; - icplb_table[j][1] = SDRAM_IGENERIC; + icplb_table[j][1] = SDRAM_INON_CHBL; #endif j = 0; dcplb_table[j][0] = 0xFF800000; @@ -220,13 +225,15 @@ void init_cplbtables(void) #if defined(CONFIG_BF561) /* MAC space */ - dcplb_table[j++][0] = CONFIG_ASYNC_EBIU_BASE; - dcplb_table[j++][1] = SDRAM_EBIU; + dcplb_table[j][0] = 0x2C000000; + dcplb_table[j][1] = SDRAM_EBIU; + j++; /* Flash space */ - for (i = 0; i < 2; i++) { - dcplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024; - dcplb_table[j++][1] = SDRAM_EBIU; + for (i = 0; i < 3; i++) { + dcplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024; + dcplb_table[j][1] = SDRAM_EBIU; + j++; } #else dcplb_table[j][0] = 0x20000000; diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c index a15914b109..9d71bcb547 100644 --- a/lib_blackfin/cache.c +++ b/lib_blackfin/cache.c @@ -1,7 +1,7 @@ /* * U-boot - cache.c * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,17 +21,15 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* for now: just dummy functions to satisfy the linker */ #include <config.h> #include <common.h> #include <asm/blackfin.h> - -extern void blackfin_icache_flush_range(unsigned long, unsigned long); -extern void blackfin_dcache_flush_range(unsigned long, unsigned long); +#include "cache.h" void flush_cache(unsigned long dummy1, unsigned long dummy2) { @@ -43,9 +41,9 @@ void flush_cache(unsigned long dummy1, unsigned long dummy2) return; if (icache_status()) - blackfin_icache_flush_range(dummy1, dummy1 + dummy2); + blackfin_icache_flush_range((void*)dummy1, (void*)(dummy1 + dummy2)); if (dcache_status()) - blackfin_dcache_flush_range(dummy1, dummy1 + dummy2); + blackfin_dcache_flush_range((void*)dummy1, (void*)(dummy1 + dummy2)); return; } diff --git a/lib_blackfin/cache.h b/lib_blackfin/cache.h new file mode 100644 index 0000000000..3ea6809d31 --- /dev/null +++ b/lib_blackfin/cache.h @@ -0,0 +1,35 @@ +/* + * U-boot - prototypes for cache handling functions. + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _LIB_BLACKFIN_CACHE_H_ +#define _LIB_BLACKFIN_CACHE_H_ + +extern void blackfin_icache_flush_range(const void *, const void *); +extern void blackfin_dcache_flush_range(const void *, const void *); +extern void blackfin_dcache_invalidate_range(const void *, const void *); + +#endif diff --git a/lib_blackfin/memcmp.S b/lib_blackfin/memcmp.S index fcea5b3daf..9b58832943 100644 --- a/lib_blackfin/memcmp.S +++ b/lib_blackfin/memcmp.S @@ -1,17 +1,8 @@ /* - * File: arch/blackfin/lib/memcmp.S - * Based on: - * Author: + * File: memcmp.S * - * Created: - * Description: - * - * Rev: $Id: memcmp.S 2386 2006-11-01 04:57:26Z magicyang $ - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * Copyright 2004-2007 Analog Devices Inc. + * Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/lib_blackfin/memcpy.S b/lib_blackfin/memcpy.S index a73ff90712..24577bebdc 100644 --- a/lib_blackfin/memcpy.S +++ b/lib_blackfin/memcpy.S @@ -1,22 +1,8 @@ /* - * File: arch/blackfin/lib/memcpy.S - * Based on: - * Author: + * File: memcpy.S * - * Created: - * Description: internal version of memcpy(), issued by the compiler - * to copy blocks of data around. - * This is really memmove() - it has to be able to deal with - * possible overlaps, because that ambiguity is when the compiler - * gives up and calls a function. We have our own, internal version - * so that we get something we trust, even if the user has redefined - * the normal symbol. - * Rev: $Id: memcpy.S 2775 2007-02-21 13:58:44Z hennerich $ - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * Copyright 2004-2007 Analog Devices Inc. + * Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,6 +19,7 @@ * to the Free Software Foundation, Inc., * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + .align 2 .globl _memcpy_ASM; diff --git a/lib_blackfin/memmove.S b/lib_blackfin/memmove.S index 79558f951e..46f79ed18d 100644 --- a/lib_blackfin/memmove.S +++ b/lib_blackfin/memmove.S @@ -1,17 +1,8 @@ /* - * File: arch/blackfin/lib/memmove.S - * Based on: - * Author: + * File: memmove.S * - * Created: - * Description: - * - * Rev: $Id: memmove.S 2205 2006-09-23 07:53:49Z vapier $ - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * Copyright 2004-2007 Analog Devices Inc. + * Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/lib_blackfin/memset.S b/lib_blackfin/memset.S index 7e6ee198eb..c33c551121 100644 --- a/lib_blackfin/memset.S +++ b/lib_blackfin/memset.S @@ -1,17 +1,8 @@ /* - * File: arch/blackfin/lib/memset.S - * Based on: - * Author: + * File: memset.S * - * Created: - * Description: - * - * Rev: $Id: memset.S 2769 2007-02-19 16:45:53Z hennerich $ - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * Copyright 2004-2007 Analog Devices Inc. + * Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +20,6 @@ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - .align 2 /* diff --git a/lib_blackfin/muldi3.c b/lib_blackfin/muldi3.c index da55711dd7..bf1ca535fa 100644 --- a/lib_blackfin/muldi3.c +++ b/lib_blackfin/muldi3.c @@ -1,7 +1,7 @@ /* * U-boot - muldi3.c contains routines for mult and div * - * Copyright (c) 2005 blackfin.uclinux.org + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ /* Generic function got from GNU gcc package, libgcc2.c */ diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index d92f14270e..b14d661bbe 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -37,6 +37,8 @@ * on our cache or tlb entries. */ +DECLARE_GLOBAL_DATA_PTR; + struct exception_table_entry { unsigned long insn, fixup; @@ -55,13 +57,25 @@ search_one_table(const struct exception_table_entry *first, long diff; mid = (last - first) / 2 + first; - diff = mid->insn - value; - if (diff == 0) - return mid->fixup; - else if (diff < 0) - first = mid+1; + if ((ulong) mid > CFG_MONITOR_BASE) { + /* exception occurs in FLASH, before u-boot relocation. + * No relocation offset is needed. + */ + diff = mid->insn - value; + if (diff == 0) + return mid->fixup; + } else { + /* exception occurs in RAM, after u-boot relocation. + * A relocation offset should be added. + */ + diff = (mid->insn + gd->reloc_off) - value; + if (diff == 0) + return (mid->fixup + gd->reloc_off); + } + if (diff < 0) + first = mid + 1; else - last = mid-1; + last = mid - 1; } return 0; } @@ -75,8 +89,11 @@ search_exception_table(unsigned long addr) /* There is only the kernel to search. */ ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); + /* if the serial port does not hang in exception, printf can be used */ +#if !defined(CFG_SERIAL_HANG_IN_EXCEPTION) if (ex_tab_message) printf("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret); +#endif if (ret) return ret; return 0; diff --git a/libfdt/fdt.c b/libfdt/fdt.c index 4b1c8abf95..212b83838c 100644 --- a/libfdt/fdt.c +++ b/libfdt/fdt.c @@ -23,7 +23,7 @@ #include "libfdt_internal.h" -int _fdt_check_header(const void *fdt) +int fdt_check_header(const void *fdt) { if (fdt_magic(fdt) == FDT_MAGIC) { /* Complete tree */ @@ -72,7 +72,7 @@ const char *_fdt_find_string(const char *strtab, int tabsize, const char *s) int fdt_move(const void *fdt, void *buf, int bufsize) { - int err = _fdt_check_header(fdt); + int err = fdt_check_header(fdt); if (err) return err; diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c index ce01dc700b..4e2c325b4d 100644 --- a/libfdt/fdt_ro.c +++ b/libfdt/fdt_ro.c @@ -25,7 +25,7 @@ #define CHECK_HEADER(fdt) { \ int err; \ - if ((err = _fdt_check_header(fdt)) != 0) \ + if ((err = fdt_check_header(fdt)) != 0) \ return err; \ } @@ -188,7 +188,7 @@ struct fdt_property *fdt_get_property(const void *fdt, int offset, nextoffset; int err; - if ((err = _fdt_check_header(fdt)) != 0) + if ((err = fdt_check_header(fdt)) != 0) goto fail; err = -FDT_ERR_BADOFFSET; @@ -329,3 +329,74 @@ uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset, char **namep return tag; } + +/* + * Return the number of used reserve map entries and total slots available. + */ +int fdt_num_reservemap(void *fdt, int *used, int *total) +{ + struct fdt_reserve_entry *re; + int start; + int end; + int err = fdt_check_header(fdt); + + if (err != 0) + return err; + + start = fdt_off_mem_rsvmap(fdt); + + /* + * Convention is that the reserve map is before the dt_struct, + * but it does not have to be. + */ + end = fdt_totalsize(fdt); + if (end > fdt_off_dt_struct(fdt)) + end = fdt_off_dt_struct(fdt); + if (end > fdt_off_dt_strings(fdt)) + end = fdt_off_dt_strings(fdt); + + /* + * Since the reserved area list is zero terminated, you get one fewer. + */ + if (total) + *total = ((end - start) / sizeof(struct fdt_reserve_entry)) - 1; + + if (used) { + *used = 0; + while (start < end) { + re = (struct fdt_reserve_entry *)(fdt + start); + if (re->size == 0) + return 0; /* zero size terminates the list */ + + *used += 1; + start += sizeof(struct fdt_reserve_entry); + } + /* + * If we get here, there was no zero size termination. + */ + return -FDT_ERR_BADLAYOUT; + } + return 0; +} + +/* + * Return the nth reserve map entry. + */ +int fdt_get_reservemap(void *fdt, int n, struct fdt_reserve_entry *re) +{ + int used; + int total; + int err; + + err = fdt_num_reservemap(fdt, &used, &total); + if (err != 0) + return err; + + if (n >= total) + return -FDT_ERR_NOSPACE; + if (re) { + *re = *(struct fdt_reserve_entry *) + _fdt_offset_ptr(fdt, n * sizeof(struct fdt_reserve_entry)); + } + return 0; +} diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c index b33fbf45de..aaafc53644 100644 --- a/libfdt/fdt_rw.c +++ b/libfdt/fdt_rw.c @@ -27,7 +27,7 @@ static int rw_check_header(void *fdt) { int err; - if ((err = _fdt_check_header(fdt))) + if ((err = fdt_check_header(fdt))) return err; if (fdt_version(fdt) < 0x11) return -FDT_ERR_BADVERSION; diff --git a/libfdt/fdt_wip.c b/libfdt/fdt_wip.c index 261b9b0dc9..2d2ed37c47 100644 --- a/libfdt/fdt_wip.c +++ b/libfdt/fdt_wip.c @@ -110,3 +110,28 @@ int fdt_nop_node(void *fdt, int nodeoffset) nop_region(fdt_offset_ptr(fdt, nodeoffset, 0), endoffset - nodeoffset); return 0; } + +/* + * Replace a reserve map entry in the nth slot. + */ +int fdt_replace_reservemap_entry(void *fdt, int n, uint64_t addr, uint64_t size) +{ + struct fdt_reserve_entry *re; + int used; + int total; + int err; + + err = fdt_num_reservemap(fdt, &used, &total); + if (err != 0) + return err; + + if (n >= total) + return -FDT_ERR_NOSPACE; + re = (struct fdt_reserve_entry *) + (fdt + fdt_off_mem_rsvmap(fdt) + + (n * sizeof(struct fdt_reserve_entry))); + re->address = cpu_to_fdt64(addr); + re->size = cpu_to_fdt64(size); + + return 0; +} @@ -52,9 +52,12 @@ extern int rtl8139_initialize(bd_t*); extern int rtl8169_initialize(bd_t*); extern int scc_initialize(bd_t*); extern int skge_initialize(bd_t*); +extern int tsi108_eth_initialize(bd_t*); extern int tsec_initialize(bd_t*, int, char *); extern int npe_initialize(bd_t *); extern int uec_initialize(int); +extern int bfin_EMAC_initialize(bd_t *); +extern int atstk1000_eth_initialize(bd_t *); static struct eth_device *eth_devices, *eth_current; @@ -249,12 +252,21 @@ int eth_initialize(bd_t *bis) #ifdef CONFIG_NS8382X ns8382x_initialize(bis); #endif +#if defined(CONFIG_TSI108_ETH) + tsi108_eth_initialize(bis); +#endif #if defined(CONFIG_RTL8139) rtl8139_initialize(bis); #endif #if defined(CONFIG_RTL8169) rtl8169_initialize(bis); #endif +#if defined(CONFIG_BF537) + bfin_EMAC_initialize(bis); +#endif +#if defined(CONFIG_ATSTK1000) + atstk1000_eth_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); @@ -1424,6 +1424,26 @@ NetReceive(volatile uchar * inpkt, int len) /* XXX point to ip packet */ (*packetHandler)((uchar *)ip, 0, 0, 0); return; + case ICMP_ECHO_REQUEST: +#ifdef ET_DEBUG + printf ("Got ICMP ECHO REQUEST, return %d bytes \n", + ETHER_HDR_SIZE + len); +#endif + memcpy (&et->et_dest[0], &et->et_src[0], 6); + memcpy (&et->et_src[ 0], NetOurEther, 6); + + ip->ip_sum = 0; + ip->ip_off = 0; + NetCopyIP((void*)&ip->ip_dst, &ip->ip_src); + NetCopyIP((void*)&ip->ip_src, &NetOurIP); + ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP >> 1); + + icmph->type = ICMP_ECHO_REPLY; + icmph->checksum = 0; + icmph->checksum = ~NetCksum((uchar *)icmph, + (len - IP_HDR_SIZE_NO_UDP) >> 1); + (void) eth_send((uchar *)et, ETHER_HDR_SIZE + len); + return; #endif default: return; |