diff options
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_sfr.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d2.h | 5 |
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index b040256ba4..b805a2c934 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -32,6 +32,30 @@ struct atmel_sfr { #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 +/* Bit field in EBICFG */ +#define AT91_SFR_EBICFG_DRIVE0 (0x3 << 0) +#define AT91_SFR_EBICFG_DRIVE0_LOW (0x0 << 0) +#define AT91_SFR_EBICFG_DRIVE0_MEDIUM (0x2 << 0) +#define AT91_SFR_EBICFG_DRIVE0_HIGH (0x3 << 0) +#define AT91_SFR_EBICFG_PULL0 (0x3 << 2) +#define AT91_SFR_EBICFG_PULL0_UP (0x0 << 2) +#define AT91_SFR_EBICFG_PULL0_NONE (0x1 << 2) +#define AT91_SFR_EBICFG_PULL0_DOWN (0x3 << 2) +#define AT91_SFR_EBICFG_SCH0 (0x1 << 4) +#define AT91_SFR_EBICFG_SCH0_OFF (0x0 << 4) +#define AT91_SFR_EBICFG_SCH0_ON (0x1 << 4) +#define AT91_SFR_EBICFG_DRIVE1 (0x3 << 8) +#define AT91_SFR_EBICFG_DRIVE1_LOW (0x0 << 8) +#define AT91_SFR_EBICFG_DRIVE1_MEDIUM (0x2 << 8) +#define AT91_SFR_EBICFG_DRIVE1_HIGH (0x3 << 8) +#define AT91_SFR_EBICFG_PULL1 (0x3 << 10) +#define AT91_SFR_EBICFG_PULL1_UP (0x0 << 10) +#define AT91_SFR_EBICFG_PULL1_NONE (0x1 << 10) +#define AT91_SFR_EBICFG_PULL1_DOWN (0x3 << 10) +#define AT91_SFR_EBICFG_SCH1 (0x1 << 12) +#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) +#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) + /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index dd5a2a7523..25c85411e5 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -135,7 +135,11 @@ /* * Address Memory Space */ +#define ATMEL_BASE_CS0 0x10000000 #define ATMEL_BASE_DDRCS 0x20000000 +#define ATMEL_BASE_CS1 0x60000000 +#define ATMEL_BASE_CS2 0x70000000 +#define ATMEL_BASE_CS3 0x80000000 #define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 #define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 #define ATMEL_BASE_SDMMC0 0xa0000000 @@ -165,6 +169,7 @@ */ #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) +#define ATMEL_BASE_SMC (ATMEL_BASE_HSMC + 0x700) #define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) #define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) |