diff options
38 files changed, 343 insertions, 152 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e644ee3e18..7b20750662 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -214,6 +214,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK ARM_SOC_BOOT0_HOOK which contains the required assembler preprocessor code. +config ARM_CORTEX_CPU_IS_UP + bool + default n + config USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy" default y diff --git a/arch/arm/cpu/arm920t/interrupts.c b/arch/arm/cpu/arm920t/interrupts.c deleted file mode 100644 index 0e04d3668b..0000000000 --- a/arch/arm/cpu/arm920t/interrupts.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/proc-armv/ptrace.h> - -#if defined (CONFIG_ARCH_INTEGRATOR) -void do_irq (struct pt_regs *pt_regs) -{ - /* ASSUMED to be a timer interrupt */ - /* Just clear it - count handled in */ - /* integratorap.c */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0; -} -#endif diff --git a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c deleted file mode 100644 index 036e3b906c..0000000000 --- a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include <asm/arch/s3c24x0_cpu.h> -#include <asm/proc-armv/ptrace.h> - -void do_irq (struct pt_regs *pt_regs) -{ - struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt(); - u_int32_t intpnd = readl(&irq->INTPND); - -} diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index 3d41d37a64..e1dc5f3748 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -37,7 +37,7 @@ .align 5 -#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define ONE_MS (COUNTER_FREQUENCY / 1000) #define RESET_WAIT (30 * ONE_MS) .globl psci_version diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index e6a32caafc..d5237d214a 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -62,7 +62,7 @@ int timer_init(void) /* Enable System Counter */ writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); - freq = GENERIC_TIMER_CLK; + freq = COUNTER_FREQUENCY; asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); /* Set PL1 Physical Timer Ctrl */ diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 95ce9387b8..e39aba7115 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -188,11 +188,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_TIMER_CLK_FREQ +#ifdef COUNTER_FREQUENCY mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_TIMER_CLK_FREQ + ldreq r1, =COUNTER_FREQUENCY mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 766b8c79d9..104dc909bc 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -46,7 +46,7 @@ static u32 __secure cp15_read_cntp_ctl(void) return val; } -#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) +#define ONE_MS (COUNTER_FREQUENCY / 1000) static void __secure __mdelay(u32 ms) { diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index bc4dc2ce79..7378c88431 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -302,6 +302,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-nanopi-neo.dtb +dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ sun50i-a64-pine64.dtb diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts new file mode 100644 index 0000000000..de60f783d3 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "sun8i-h3.dtsi" + +/ { + model = "OrangePi PC 2"; + compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5"; + + cpus { + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x40000000 0x40000000>; + }; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + }; + + soc { + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; +}; + +&gic { + compatible = "arm,gic-400"; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 0>; + cd-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-mode = "rgmii"; + phy = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 3f87672c62..1bfb48bd52 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -242,7 +242,7 @@ struct sunxi_ccm_reg { /* ahb_gate0 offsets */ #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 -#ifdef CONFIG_MACH_SUN8I_H3 +#ifdef CONFIG_MACH_SUNXI_H3_H5 /* * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call * them 0 - 2 like they were called on older SoCs. @@ -293,7 +293,7 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) -#ifdef CONFIG_MACH_SUN8I_H3 +#ifdef CONFIG_MACH_SUNXI_H3_H5 /* * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call * them 0 - 2 like they were called on older SoCs. diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 6f96a9715a..e8e670e7e9 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -15,5 +15,6 @@ #define SOCID_A64 0x1689 #define SOCID_H3 0x1680 +#define SOCID_H5 0x1718 #endif /* _SUNXI_CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 3c852224e6..ea672fe844 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -56,7 +56,7 @@ #define SUNXI_USB2_BASE 0x01c1c000 #endif #ifdef CONFIG_SUNXI_GEN_SUN6I -#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I) +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_USBPHY_BASE 0x01c19000 #define SUNXI_USB0_BASE 0x01c1a000 #define SUNXI_USB1_BASE 0x01c1b000 @@ -94,7 +94,7 @@ #define SUNXI_KEYPAD_BASE 0x01c23000 #define SUNXI_TZPC_BASE 0x01c23400 -#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \ +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ defined(CONFIG_MACH_SUN50I) /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ #define SUNXI_SIDC_BASE 0x01c14000 diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 53e6d471d2..1dc82205b7 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,7 +24,7 @@ #include <asm/arch/dram_sun8i_a33.h> #elif defined(CONFIG_MACH_SUN8I_A83T) #include <asm/arch/dram_sun8i_a83t.h> -#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I) +#elif defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #include <asm/arch/dram_sun8i_h3.h> #elif defined(CONFIG_MACH_SUN9I) #include <asm/arch/dram_sun9i.h> diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index 5d7ab559ef..831d0c0ff6 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -12,7 +12,7 @@ #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ #define SPL_HEADER_VERSION 1 -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) +#ifdef CONFIG_SUNXI_HIGH_SRAM #define SPL_ADDR 0x10000 #else #define SPL_ADDR 0x0 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 7daba1169c..efab4811ee 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,7 +48,7 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o +obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 52be5b0551..5e03d03943 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -40,7 +40,7 @@ struct fel_stash { struct fel_stash fel_stash __attribute__((section(".data"))); -#ifdef CONFIG_MACH_SUN50I +#ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> static struct mm_region sunxi_mem_map[] = { @@ -98,7 +98,7 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3) +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); @@ -180,15 +180,13 @@ void s_init(void) /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ #endif -#if defined CONFIG_MACH_SUN6I || \ - defined CONFIG_MACH_SUN7I || \ - defined CONFIG_MACH_SUN8I || \ - defined CONFIG_MACH_SUN9I +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); + "mcr p15, 0, r0, c1, c0, 1\n" + ::: "r0"); #endif #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index d123b3acb2..4762fbf0c3 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -22,7 +22,7 @@ void clock_init_safe(void) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -#if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I) +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) struct sunxi_prcm_reg * const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; @@ -51,7 +51,7 @@ void clock_init_safe(void) void clock_init_sec(void) { -#ifdef CONFIG_MACH_SUN8I_H3 +#ifdef CONFIG_MACH_SUNXI_H3_H5 struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; @@ -152,7 +152,7 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) const int max_n = 32; int k = 1, m = 2; -#ifdef CONFIG_MACH_SUN8I_H3 +#ifdef CONFIG_MACH_SUNXI_H3_H5 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | CCM_PLL5_TUN_INIT_FREQ_MASK, CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index f1f6fd5ba4..85633ccec2 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -91,6 +91,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A80 (SUN9I)\n"); #elif defined CONFIG_MACH_SUN50I puts("CPU: Allwinner A64 (SUN50I)\n"); +#elif defined CONFIG_MACH_SUN50I_H5 + puts("CPU: Allwinner H5 (SUN50I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c index 9f7cc7fd4c..d681a9df8b 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void) writel(0x81000004, &mctl_com->mdfs_bwlr[2]); } +static void mctl_set_master_priority_h5(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + + /* enable bandwidth limit windows and set windows size 1us */ + writel(399, &mctl_com->tmr); + writel((1 << 16), &mctl_com->bwcr); + + /* set cpu high priority */ + writel(0x00000001, &mctl_com->mapr); + + /* Port 2 is reserved per Allwinner's linux-3.10 source, yet + * they initialise it */ + MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150); + MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200); + MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96); + MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32); + MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000); + MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100); + MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64); + MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64); + MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64); + MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64); + MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024); + MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200); +} + static void mctl_set_master_priority(uint16_t socid) { switch (socid) { @@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid) case SOCID_A64: mctl_set_master_priority_a64(); return; + case SOCID_H5: + mctl_set_master_priority_h5(); + return; } } @@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) /* set two rank timing */ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), - (0x66 << 8) | (0x10 << 0)); + ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0)); /* set PHY interface timing, write latency and read latency configure */ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | @@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para) CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL11 | CCM_DRAMCLK_CFG_UPD); - } else if (socid == SOCID_H3) { + } else if (socid == SOCID_H3 || socid == SOCID_H5) { clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK | @@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para) setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); udelay(10); - writel(0xc00e, &mctl_ctl->clken); + writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken); udelay(500); } @@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* setting VTC, default disable all VT */ clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); - clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); + if (socid == SOCID_H5) + setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26)); + else + clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); /* increase DFI_PHY_UPD clock */ writel(PROTECT_MAGIC, &mctl_com->protect); @@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) udelay(100); /* set dramc odt */ - for (i = 0; i < 4; i++) - clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) | - (0x1 << 1) | (0x3 << 2) | (0x3 << 12) | - (0x3 << 14), - IS_ENABLED(CONFIG_DRAM_ODT_EN) ? - DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF); + for (i = 0; i < 4; i++) { + u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) | + (0x3 << 12) | (0x3 << 14); + u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ? + DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF; + + if (socid == SOCID_H5) { + clearmask |= 0x2 << 8; + setmask |= 0x4 << 8; + } + clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); + } /* AC PDR should always ON */ - setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); + clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0, + 0x1 << 1); /* set DQS auto gating PD mode */ setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); @@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* dphy & aphy phase select 270 degree */ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), (0x1 << 10) | (0x2 << 8)); - } else if (socid == SOCID_A64) { + } else if (socid == SOCID_A64 || socid == SOCID_H5) { /* dphy & aphy phase select ? */ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), (0x0 << 10) | (0x3 << 8)); @@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE); - } else if (socid == SOCID_A64) { + } else if (socid == SOCID_A64 || socid == SOCID_H5) { clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE); + /* no PIR_QSGATE for H5 ???? */ } /* detect ranks and bus width */ @@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* set PGCR3, CKE polarity */ if (socid == SOCID_H3) writel(0x00aa0060, &mctl_ctl->pgcr[3]); - else if (socid == SOCID_A64) + else if (socid == SOCID_A64 || socid == SOCID_H5) writel(0xc0aa0060, &mctl_ctl->pgcr[3]); /* power down zq calibration module for power save */ @@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) 3, 4, 0, 3, 4, 1, 4, 0, \ 1, 1, 0, 1, 13, 5, 4 } +#define SUN8I_H5_DX_READ_DELAYS \ + {{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \ + { 21, 21, 12, 22, 21, 21, 21, 21, 21, 3, 3 }, \ + { 16, 19, 19, 17, 22, 22, 21, 22, 19, 3, 3 }, \ + { 21, 21, 22, 22, 20, 21, 19, 19, 19, 3, 3 } } +#define SUN8I_H5_DX_WRITE_DELAYS \ + {{ 1, 2, 3, 4, 3, 4, 4, 4, 6, 6, 6 }, \ + { 6, 6, 6, 5, 5, 5, 5, 5, 6, 6, 6 }, \ + { 0, 2, 4, 2, 6, 5, 5, 5, 6, 6, 6 }, \ + { 3, 3, 3, 2, 2, 1, 1, 1, 4, 4, 4 } } +#define SUN8I_H5_AC_DELAYS \ + { 0, 0, 5, 5, 0, 0, 0, 0, \ + 0, 0, 0, 0, 3, 3, 3, 3, \ + 3, 3, 3, 3, 3, 3, 3, 3, \ + 3, 3, 3, 3, 2, 0, 0 } + unsigned long sunxi_dram_init(void) { struct sunxi_mctl_com_reg * const mctl_com = @@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void) .dx_read_delays = SUN50I_A64_DX_READ_DELAYS, .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS, .ac_delays = SUN50I_A64_AC_DELAYS, +#elif defined(CONFIG_MACH_SUN50I_H5) + .dx_read_delays = SUN8I_H5_DX_READ_DELAYS, + .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS, + .ac_delays = SUN8I_H5_AC_DELAYS, #endif }; /* @@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void) uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN50I) uint16_t socid = SOCID_A64; +#elif defined(CONFIG_MACH_SUN50I_H5) + uint16_t socid = SOCID_H5; #endif mctl_sys_init(socid, ¶); @@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void) if (socid == SOCID_H3) writel(0x0c000400, &mctl_ctl->odtcfg); - if (socid == SOCID_A64) { - setbits_le32(&mctl_ctl->vtfcr, 2 << 8); + if (socid == SOCID_A64 || socid == SOCID_H5) { + setbits_le32(&mctl_ctl->vtfcr, + (socid == SOCID_H5 ? 3 : 2) << 8); clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13)); } diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 278587b493..9bf0b5633d 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -146,10 +146,10 @@ __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, } } -#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I) +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy) { -#if defined CONFIG_MACH_SUN8I_H3 +#if defined CONFIG_MACH_SUNXI_H3_H5 if (phy->id == 0) clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01); #endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 37b42521a4..3e0e262473 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -27,6 +27,17 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y +config SUNXI_HIGH_SRAM + bool + default n + ---help--- + Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, + with the first SRAM region being located at address 0. + Some newer SoCs map the boot ROM at address 0 instead and move the + SRAM to 64KB, just behind the mask ROM. + Chips using the latter setup are supposed to select this option to + adjust the addresses accordingly. + # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig config SUNXI_GEN_SUN4I @@ -43,6 +54,11 @@ config SUNXI_GEN_SUN6I watchdog, etc. +config MACH_SUNXI_H3_H5 + bool + select SUNXI_GEN_SUN6I + select SUPPORT_SPL + choice prompt "Sunxi SoC Variant" optional @@ -50,12 +66,14 @@ choice config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7 + select ARM_CORTEX_CPU_IS_UP select SUNXI_GEN_SUN4I select SUPPORT_SPL config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7 + select ARM_CORTEX_CPU_IS_UP select SUNXI_GEN_SUN4I select SUPPORT_SPL @@ -111,13 +129,13 @@ config MACH_SUN8I_H3 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI - select SUNXI_GEN_SUN6I - select SUPPORT_SPL + select MACH_SUNXI_H3_H5 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN9I bool "sun9i (Allwinner A80)" select CPU_V7 + select SUNXI_HIGH_SRAM select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -125,14 +143,21 @@ config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 select SUNXI_GEN_SUN6I + select SUNXI_HIGH_SRAM select SUPPORT_SPL +config MACH_SUN50I_H5 + bool "sun50i (Allwinner H5)" + select ARM64 + select MACH_SUNXI_H3_H5 + select SUNXI_HIGH_SRAM + endchoice # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" config MACH_SUN8I bool - default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T + default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T config RESERVE_ALLWINNER_BOOT0_HEADER bool "reserve space for Allwinner boot0 header" @@ -320,7 +345,7 @@ config OLD_SUNXI_KERNEL_COMPAT config MMC0_CD_PIN string "Card detect pin for mmc0" - default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I + default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I default "" ---help--- Set the card detect pin for mmc0, leave empty to not use cd. This @@ -485,7 +510,7 @@ config AXP_GPIO config VIDEO bool "Enable graphical uboot console on HDMI, LCD or VGA" - depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I + depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I default y ---help--- Say Y here to add support for using a cfb console on the HDMI, LCD diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 2321b8b08f..3f211293fe 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -242,6 +242,11 @@ M: Icenowy Zheng <icenowy@aosc.xyz> S: Maintained F: configs/orangepi_zero_defconfig +ORANGEPI PC 2 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/orangepi_pc2_defconfig + R16 EVB PARROT BOARD M: Quentin Schulz <quentin.schulz@free-electrons.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 53656383d5..b9660128e5 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -100,14 +100,14 @@ int board_init(void) * we avoid the risk of writing to it. */ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); - if (freq != CONFIG_TIMER_CLK_FREQ) { + if (freq != COUNTER_FREQUENCY) { debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", - freq, CONFIG_TIMER_CLK_FREQ); + freq, COUNTER_FREQUENCY); #ifdef CONFIG_NON_SECURE printf("arch timer frequency is wrong, but cannot adjust it\n"); #else asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(CONFIG_TIMER_CLK_FREQ)); + : : "r"(COUNTER_FREQUENCY)); #endif } } diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index e14cb9d80e..201771ee8f 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig new file mode 100644 index 0000000000..19a5c2b882 --- /dev/null +++ b/configs/orangepi_pc2_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_SPL=y +CONFIG_DRAM_CLK=672 +CONFIG_DRAM_ZQ=3881977 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 1f23c8e34e..5ca0a712d8 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -132,7 +132,7 @@ if SPL config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_H3 || MACH_SUN50I + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I ---help--- Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c index a24c115174..852abd41de 100644 --- a/drivers/mtd/spi/sunxi_spi_spl.c +++ b/drivers/mtd/spi/sunxi_spi_spl.c @@ -185,14 +185,14 @@ static void spi0_deinit(void) #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, - u32 spi_ctl_reg, - u32 spi_ctl_xch_bitmask, - u32 spi_fifo_reg, - u32 spi_tx_reg, - u32 spi_rx_reg, - u32 spi_bc_reg, - u32 spi_tc_reg, - u32 spi_bcc_reg) + ulong spi_ctl_reg, + ulong spi_ctl_xch_bitmask, + ulong spi_fifo_reg, + ulong spi_tx_reg, + ulong spi_rx_reg, + ulong spi_bc_reg, + ulong spi_tc_reg, + ulong spi_bcc_reg) { writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index b87210bad7..abdfada646 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -62,7 +62,7 @@ #define AHB_GATE_OFFSET_EPHY 0 -#if defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUNXI_H3_H5) #define SUN8I_GPD8_GMAC 2 #else #define SUN8I_GPD8_GMAC 4 diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index f2c5629be2..64e5bc2f74 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -12,7 +12,7 @@ choice default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 default AXP818_POWER if MACH_SUN8I_A83T - default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I + default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I config SUNXI_NO_PMIC bool "board without a pmic" @@ -60,7 +60,7 @@ config AXP818_POWER config SY8106A_POWER bool "SY8106A pmic support" - depends on MACH_SUN8I_H3 + depends on MACH_SUNXI_H3_H5 ---help--- Select this to enable support for the SY8106A pmic found on some H3 boards. diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 5bb97ff45b..068f24f483 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -45,7 +45,7 @@ static int ehci_usb_probe(struct udevice *dev) * clocks resp. phys. */ priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; -#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I) +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index b4f75302db..ade66a4330 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -23,7 +23,7 @@ /* input clock of PLL: 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 -#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index db29fa2ba1..dfb72384d3 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -36,11 +36,6 @@ #define CONFIG_CMD_EXT2 #endif -/* - * Generic Timer Definitions - */ -#define GENERIC_TIMER_CLK 12500000 - #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 @@ -243,7 +238,7 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_TIMER_CLK_FREQ 12500000 +#define COUNTER_FREQUENCY 12500000 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4fb8b0ca8c..15850f2b52 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -27,11 +27,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE -/* - * Generic Timer Definitions - */ -#define GENERIC_TIMER_CLK 12500000 - #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); @@ -500,7 +495,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_TIMER_CLK_FREQ 12500000 +#define COUNTER_FREQUENCY 12500000 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index c6438d5ec6..5d6a64acbd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -56,11 +56,6 @@ #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif -/* - * Generic Timer Definitions - */ -#define GENERIC_TIMER_CLK 12500000 - #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 @@ -370,7 +365,7 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_TIMER_CLK_FREQ 12500000 +#define COUNTER_FREQUENCY 12500000 #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 5bf8ad74b8..e2b05caa94 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SYSCOUNTER_TIMER #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK +#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK #define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_BOOTM_LEN 0x1000000 diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 3e5708b493..1b7bfb6c22 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -18,7 +18,6 @@ #define CONFIG_SUNXI_USB_PHYS 1 -#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 05ea172fe3..377ae00a7b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -46,7 +46,7 @@ #endif /* CPU */ -#define CONFIG_TIMER_CLK_FREQ 24000000 +#define COUNTER_FREQUENCY 24000000 /* * The DRAM Base differs between some models. We cannot use macros for the @@ -79,7 +79,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) +#ifdef CONFIG_SUNXI_HIGH_SRAM /* * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is * slightly bigger. Note that it is possible to map the first 32 KiB of the @@ -175,32 +175,24 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #endif -#if defined(CONFIG_MACH_SUN9I) +#ifdef CONFIG_SUNXI_HIGH_SRAM #define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* ? KiB on sun9i */ -#elif defined(CONFIG_MACH_SUN50I) -#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB on sun50i */ +#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB */ +#define LOW_LEVEL_SRAM_STACK 0x00018000 #else #define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #endif +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + #ifndef CONFIG_ARM64 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" #endif #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) -/* FIXME: 40 KiB instead of 32 KiB ? */ -#define LOW_LEVEL_SRAM_STACK 0x00018000 -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#else -/* end of 32 KiB in sram */ -#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#endif /* I2C */ #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7fdab589e3..811ba91d95 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -6305,7 +6305,6 @@ CONFIG_TI816X_EVM_DDR3 CONFIG_TI816X_USE_EMIF0 CONFIG_TI816X_USE_EMIF1 CONFIG_TI81XX -CONFIG_TIMER_CLK_FREQ CONFIG_TIMESTAMP CONFIG_TIZEN CONFIG_TI_KEYSTONE_SERDES |