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Diffstat (limited to 'arch/arc/lib/start.S')
-rw-r--r--arch/arc/lib/start.S46
1 files changed, 37 insertions, 9 deletions
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index e1ef19cb88..26a5934189 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -13,18 +13,46 @@ ENTRY(_start)
/* Setup interrupt vector base that matches "__text_start" */
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
- /* Setup stack- and frame-pointers */
- mov %sp, CONFIG_SYS_INIT_SP_ADDR
- mov %fp, %sp
+ ; Disable/enable I-cache according to configuration
+ lr r5, [ARC_BCR_IC_BUILD]
+ breq r5, 0, 1f ; I$ doesn't exist
+ lr r5, [ARC_AUX_IC_CTRL]
+#ifndef CONFIG_SYS_ICACHE_OFF
+ bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
+#else
+ bset r5, r5, 0 ; I$ exists, but is not used
+#endif
+ sr r5, [ARC_AUX_IC_CTRL]
+
+1:
+ ; Disable/enable D-cache according to configuration
+ lr r5, [ARC_BCR_DC_BUILD]
+ breq r5, 0, 1f ; D$ doesn't exist
+ lr r5, [ARC_AUX_DC_CTRL]
+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
+#ifndef CONFIG_SYS_DCACHE_OFF
+ bclr r5, r5, 0 ; Enable (+Inv)
+#else
+ bset r5, r5, 0 ; Disable (+Inv)
+#endif
+ sr r5, [ARC_AUX_DC_CTRL]
- /* Unconditionally disable caches */
+1:
#ifdef CONFIG_ISA_ARCV2
- bl slc_flush
- bl slc_disable
+ ; Disable System-Level Cache (SLC)
+ lr r5, [ARC_BCR_SLC]
+ breq r5, 0, 1f ; SLC doesn't exist
+ lr r5, [ARC_AUX_SLC_CTRL]
+ bclr r5, r5, 6 ; Invalidate (discard w/o wback)
+ bclr r5, r5, 0 ; Enable (+Inv)
+ sr r5, [ARC_AUX_SLC_CTRL]
+
+1:
#endif
- bl flush_dcache_all
- bl dcache_disable
- bl icache_disable
+
+ /* Setup stack- and frame-pointers */
+ mov %sp, CONFIG_SYS_INIT_SP_ADDR
+ mov %fp, %sp
/* Allocate and zero GD, update SP */
mov %r0, %sp