diff options
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/dts/axs10x_mb.dtsi | 34 | ||||
| -rw-r--r-- | arch/arc/dts/hsdk.dts | 7 | ||||
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 3 | ||||
| -rw-r--r-- | arch/arc/lib/start.S | 9 |
4 files changed, 52 insertions, 1 deletions
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index 3855a34dc2..dfc03810ca 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -4,6 +4,10 @@ */ / { + aliases { + spi0 = &spi0; + }; + axs10x_mb@e0000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -56,5 +60,35 @@ reg-shift = <2>; reg-io-width = <4>; }; + + spi0: spi@0 { + compatible = "snps,dw-apb-ssi"; + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <4000000>; + clocks = <&apbclk>; + clock-names = "spi_clk"; + cs-gpio = <&cs_gpio 0>; + spi_flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <4000000>; + }; + }; + + cs_gpio: gpio@11218 { + compatible = "snps,creg-gpio"; + reg = <0x11218 0x4>; + gpio-controller; + #gpio-cells = <1>; + gpio-bank-name = "axs-spi-cs"; + gpio-count = <1>; + gpio-first-shift = <0>; + gpio-bit-per-line = <2>; + gpio-activate-val = <1>; + gpio-deactivate-val = <3>; + gpio-default-val = <1>; + }; }; }; diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index 264512877e..e41e4ce84b 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -101,11 +101,16 @@ }; cs_gpio: gpio@f00014b0 { - compatible = "snps,hsdk-creg-gpio"; + compatible = "snps,creg-gpio"; reg = <0xf00014b0 0x4>; gpio-controller; #gpio-cells = <1>; gpio-bank-name = "hsdk-spi-cs"; gpio-count = <1>; + gpio-first-shift = <0>; + gpio-bit-per-line = <2>; + gpio-activate-val = <2>; + gpio-deactivate-val = <3>; + gpio-default-val = <1>; }; }; diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 56ec11f789..9920d2e719 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -19,6 +19,9 @@ #define ARC_AUX_IDENTITY 0x04 #define ARC_AUX_STATUS32 0x0a +/* STATUS32 Bits Positions */ +#define STATUS_AD_BIT 19 /* Enable unaligned access */ + /* Instruction cache related auxiliary registers */ #define ARC_AUX_IC_IVIC 0x10 #define ARC_AUX_IC_CTRL 0x11 diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index e573ce7718..84959b41bd 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -61,6 +61,15 @@ ENTRY(_start) 1: #endif +#ifdef __ARC_UNALIGNED__ + /* + * Enable handling of unaligned access in the CPU as by default + * this HW feature is disabled while GCC starting from 8.1.0 + * unconditionally uses it for ARC HS cores. + */ + flag 1 << STATUS_AD_BIT +#endif + /* Establish C runtime stack and frame */ mov %sp, CONFIG_SYS_INIT_SP_ADDR mov %fp, %sp |