2 files changed, 65 insertions, 38 deletions

diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index d2bddb589a..fc332fb626 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -16,6 +16,12 @@
 #include <asm/arch/spr_syscntl.h>
 #include <linux/mtd/st_smi.h>
 
+/* Reserve some space to store the BootROM's stack pointer during SPL operation.
+ * The BSS cannot be used for this purpose because it will be zeroed after
+ * having stored the pointer, so force the location to the data section.
+ */
+u32 bootrom_stash_sp __attribute__((section(".data")));
+
 static void ddr_clock_init(void)
 {
 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -223,8 +229,9 @@ u32 spl_boot_device(void)
 {
 	u32 mode = 0;
 
-	/* Currently only SNOR is supported as the only */
-	if (snor_boot_selected()) {
+	if (usb_boot_selected()) {
+		mode = BOOT_DEVICE_BOOTROM;
+	} else if (snor_boot_selected()) {
 		/* SNOR-SMI initialization */
 		snor_init();
 
@@ -234,6 +241,18 @@ u32 spl_boot_device(void)
 	return mode;
 }
 
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	/*
+	 * If the main boot device (eg. NOR) is empty, try to jump back into the
+	 * BootROM for USB boot process.
+	 */
+	if (USB_BOOT_SUPPORTED)
+		spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
+}
+
 void board_init_f(ulong dummy)
 {
 	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
@@ -251,6 +270,28 @@ void board_init_f(ulong dummy)
 	puts("Configure DDR\n");
 	mpmc_init();
 	spear_late_init();
+}
 
-	board_init_r(NULL, 0);
+/*
+ * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
+ * BootROM code right after having initialized a few components like the DRAM).
+ * The following function is called from SPL common code (board_init_r).
+ */
+void board_return_to_bootrom(void)
+{
+	/*
+	 * Retrieve the BootROM's stack pointer and jump back to the start of
+	 * the SPL, where we can easily branch back into the BootROM. Don't do
+	 * it right here because SPL might be compiled in Thumb mode while the
+	 * BootROM expects ARM mode.
+	 */
+	asm volatile ("ldr r0, =bootrom_stash_sp;"
+		      "ldr r0, [r0];"
+		      "mov sp, r0;"
+#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
+		      "blx back_to_bootrom;"
+#else
+		      "bl back_to_bootrom;"
+#endif
+		      );
 }
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
index 1cab4ca6fb..9ac96291b7 100644
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -21,51 +21,35 @@
  *
  * Startup Code (reset vector)
  *
- * Below are the critical initializations already taken place in BootROM.
- * So, these are not taken care in Xloader
- * 1. Relocation to RAM
- * 2. Initializing stacks
+ * The BootROM already initialized its own stack in the [0-0xb00] reserved
+ * range of the SRAM. The SPL (in _main) will update the stack pointer to
+ * its own SRAM area (right before the gd section).
  *
  *************************************************************************
  */
 
 	.globl	reset
+	.globl	back_to_bootrom
 
 reset:
-/*
- * Xloader has to return back to BootROM in a few cases.
- * eg. Ethernet boot, UART boot, USB boot
- * Saving registers for returning back
- */
-	stmdb	sp!, {r0-r12,r14}
-	bl	cpu_init_crit
-/*
- * Clearing bss area is not done in Xloader.
- * BSS area lies in the DDR location which is not yet initialized
- * bss is assumed to be uninitialized.
- */
-	ldmia	sp!, {r0-r12,pc}
+	/*
+	* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
+	* UART boot, USB boot): save registers in BootROM's stack and then the
+	* BootROM's stack pointer in the SPL's data section.
+	*/
+	push	{r0-r12,lr}
+	ldr	r0, =bootrom_stash_sp
+	str	sp, [r0]
 
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-cpu_init_crit:
 	/*
-	 * flush v4 I/D caches
+	 * Flush v4 I/D caches
 	 */
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+	mcr	p15, 0, r0, c7, c7, 0	/* Flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* Flush v4 TLB */
 
 	/*
-	 * enable instruction cache
+	 * Enable instruction cache
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
@@ -73,7 +57,9 @@ cpu_init_crit:
 
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
+	 * This call is not supposed to return.
 	 */
-	stmdb	sp!, {lr}
-	bl	_main	/* _main will call board_init_f */
-	ldmia	sp!, {pc}
+	b	_main	/* _main will call board_init_f */
+
+back_to_bootrom:
+	pop	{r0-r12,pc}