diff options
Diffstat (limited to 'arch/arm/cpu/armv7/keystone/ddr3.c')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/ddr3.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index 4875db76a3..2391e794e8 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -7,10 +7,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <asm/arch/hardware.h> #include <asm/io.h> +#include <common.h> +#include <asm/arch/ddr3.h> -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) { unsigned int tmp; @@ -57,7 +58,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) ; } -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) { __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); @@ -67,3 +68,21 @@ void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); } + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(KS2_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, KS2_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(KS2_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, KS2_DDR3APLLCTL1); +} |