diff options
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index fadfce4f05..20e2b1a50a 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -2,9 +2,14 @@ config ARCH_LS1021A bool select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_HAS_CCI400 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -49,9 +54,40 @@ config SECURE_BOOT Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. +config SYS_CCI400_OFFSET + hex "Offset for CCI400 base" + depends on SYS_FSL_HAS_CCI400 + default 0x180000 + help + Offset for CCI400 base. + CCI400 base addr = CCSRBAR + CCI400_OFFSET + +config SYS_FSL_ERRATUM_A008997 + bool + help + Workaround for USB PHY erratum A008997 + +config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007 + +config SYS_FSL_ERRATUM_A009008 + bool + help + Workaround for USB PHY erratum A009008 + +config SYS_FSL_ERRATUM_A009798 + bool + help + Workaround for USB PHY erratum A009798 + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_SRDS_1 bool |