diff options
Diffstat (limited to 'arch/arm/cpu/armv7/sunxi')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/Makefile | 20 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/board.c | 20 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/cpu_info.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram.c | 34 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/pinmux.c | 32 |
6 files changed, 64 insertions, 54 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 24f1daee64..82dbf764e4 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,13 +11,13 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o obj-y += pinmux.o -obj-$(CONFIG_SUN6I) += prcm.o -obj-$(CONFIG_SUN8I) += prcm.o -obj-$(CONFIG_SUN4I) += clock_sun4i.o -obj-$(CONFIG_SUN5I) += clock_sun4i.o -obj-$(CONFIG_SUN6I) += clock_sun6i.o -obj-$(CONFIG_SUN7I) += clock_sun4i.o -obj-$(CONFIG_SUN8I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN6I) += prcm.o +obj-$(CONFIG_MACH_SUN8I) += prcm.o +obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o @@ -27,9 +27,9 @@ endif endif ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SUN4I) += dram.o -obj-$(CONFIG_SUN5I) += dram.o -obj-$(CONFIG_SUN7I) += dram.o +obj-$(CONFIG_MACH_SUN4I) += dram.o +obj-$(CONFIG_MACH_SUN5I) += dram.o +obj-$(CONFIG_MACH_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 06eb6768e8..6c812fc6e9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -51,7 +51,7 @@ u32 spl_boot_mode(void) int gpio_init(void) { #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); @@ -59,23 +59,23 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPF(4), 1); -#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I) +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX); sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); @@ -88,7 +88,7 @@ int gpio_init(void) void reset_cpu(ulong addr) { -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) static const struct sunxi_wdog *wdog = &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; @@ -100,7 +100,7 @@ void reset_cpu(ulong addr) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } -#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */ +#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */ static const struct sunxi_wdog *wdog = ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; @@ -114,8 +114,8 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \ - defined CONFIG_SUN6I || defined CONFIG_SUN8I) +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \ + defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 4a0d64fb30..a0e49d179f 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -35,7 +35,7 @@ void clock_init_safe(void) APB0_DIV_1 << APB0_DIV_SHIFT | CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 4f2a09cd2e..41b9add297 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -13,9 +13,9 @@ #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I puts("CPU: Allwinner A10 (SUN4I)\n"); -#elif defined CONFIG_SUN5I +#elif defined CONFIG_MACH_SUN5I u32 val = readl(SUNXI_SID_BASE + 0x08); switch ((val >> 12) & 0xf) { case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; @@ -23,11 +23,11 @@ int print_cpuinfo(void) case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; default: puts("CPU: Allwinner A1X (SUN5I)\n"); } -#elif defined CONFIG_SUN6I +#elif defined CONFIG_MACH_SUN6I puts("CPU: Allwinner A31 (SUN6I)\n"); -#elif defined CONFIG_SUN7I +#elif defined CONFIG_MACH_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); -#elif defined CONFIG_SUN8I +#elif defined CONFIG_MACH_SUN8I puts("CPU: Allwinner A23 (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 3cf3cbf19a..dc9fdb930b 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -74,7 +74,7 @@ static void mctl_ddr3_reset(void) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I struct sunxi_timer_reg *timer = (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; u32 reg_val; @@ -113,7 +113,7 @@ static void mctl_set_drive(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), #else clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), @@ -202,7 +202,7 @@ static void mctl_enable_dllx(u32 phase) } static u32 hpcr_value[32] = { -#ifdef CONFIG_SUN5I +#ifdef CONFIG_MACH_SUN5I 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -212,7 +212,7 @@ static u32 hpcr_value[32] = { 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0 #endif -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, 0, 0, 0, 0, @@ -222,7 +222,7 @@ static u32 hpcr_value[32] = { 0x1035, 0x1031, 0x0731, 0x1035, 0x1031, 0x0301, 0x0301, 0x0731 #endif -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, 0, 0, @@ -304,7 +304,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) /* reset GPS */ clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); @@ -318,7 +318,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) /* PLL5P and PLL6 are the potential clock sources for MBUS */ pll6x_clk = clock_get_pll6() / 1000000; -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */ #endif pll5p_clk = clock_get_pll5p() / 1000000; @@ -348,7 +348,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) * open DRAMC AHB & DLL register clock * close it first */ -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); #else clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); @@ -356,7 +356,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk) udelay(22); /* then open it */ -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); #else setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); @@ -417,7 +417,7 @@ static int dramc_scan_readpipe(void) static void dramc_clock_output_en(u32 on) { -#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) +#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; if (on) @@ -425,7 +425,7 @@ static void dramc_clock_output_en(u32 on) else clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); #endif -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; if (on) setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); @@ -527,7 +527,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) u32 reg_val; u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF; -#ifndef CONFIG_SUN7I +#ifndef CONFIG_MACH_SUN7I /* Appears that some kind of automatically initiated default * ZQ calibration is already in progress at this point on sun4i/sun5i * hardware, but not on sun7i. So it is reasonable to wait for its @@ -539,7 +539,7 @@ static void mctl_set_impedance(u32 zq, u32 odt_en) if (!odt_en) return; -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock * unless bit 24 is set in SDR_ZQCR1. Not much is known about the * SDR_ZQCR1 register, but there are hints indicating that it might @@ -597,7 +597,7 @@ static unsigned long dramc_init_helper(struct dram_para *para) /* dram clock off */ dramc_clock_output_en(0); -#ifdef CONFIG_SUN4I +#ifdef CONFIG_MACH_SUN4I /* select dram controller 1 */ writel(DRAM_CSEL_MAGIC, &dram->csel); #endif @@ -654,7 +654,7 @@ static unsigned long dramc_init_helper(struct dram_para *para) writel(para->tpr2, &dram->tpr2); reg_val = DRAM_MR_BURST_LENGTH(0x0); -#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)) +#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)) reg_val |= DRAM_MR_POWER_DOWN; #endif reg_val |= DRAM_MR_CAS_LAT(para->cas - 4); @@ -668,7 +668,7 @@ static unsigned long dramc_init_helper(struct dram_para *para) /* disable drift compensation and set passive DQS window mode */ clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); -#ifdef CONFIG_SUN7I +#ifdef CONFIG_MACH_SUN7I /* Command rate timing mode 2T & 1T */ if (para->tpr4 & 0x1) setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T); @@ -718,7 +718,7 @@ unsigned long dramc_init(struct dram_para *para) /* try to autodetect the DRAM bus width and density */ para->io_width = 16; para->bus_width = 32; -#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */ para->density = 4096; #else diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c index 1f2843fcac..b026f78ca5 100644 --- a/arch/arm/cpu/armv7/sunxi/pinmux.c +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c @@ -10,32 +10,42 @@ #include <asm/io.h> #include <asm/arch/gpio.h> -int sunxi_gpio_set_cfgpin(u32 pin, u32 val) +void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) { - u32 bank = GPIO_BANK(pin); - u32 index = GPIO_CFG_INDEX(pin); - u32 offset = GPIO_CFG_OFFSET(pin); - struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); - - return 0; } -int sunxi_gpio_get_cfgpin(u32 pin) +void sunxi_gpio_set_cfgpin(u32 pin, u32 val) { - u32 cfg; u32 bank = GPIO_BANK(pin); - u32 index = GPIO_CFG_INDEX(pin); - u32 offset = GPIO_CFG_OFFSET(pin); struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + sunxi_gpio_set_cfgbank(pio, pin, val); +} + +int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) +{ + u32 index = GPIO_CFG_INDEX(bank_offset); + u32 offset = GPIO_CFG_OFFSET(bank_offset); + u32 cfg; + cfg = readl(&pio->cfg[0] + index); cfg >>= offset; return cfg & 0xf; } +int sunxi_gpio_get_cfgpin(u32 pin) +{ + u32 bank = GPIO_BANK(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + return sunxi_gpio_get_cfgbank(pio, pin); +} + int sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); |