1 files changed, 0 insertions, 78 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 5b91446a8d..62dd275f7e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -364,82 +364,6 @@ struct vcores_data omap5430_volts_es2 = {
 	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
-struct vcores_data dra752_volts = {
-	.mpu.value	= VDD_MPU_DRA7,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
-	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
-	.mpu.pmic	= &tps659038,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-	.eve.value	= VDD_EVE_DRA7,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
-	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
-	.eve.pmic	= &tps659038,
-	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-	.gpu.value	= VDD_GPU_DRA7,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
-	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
-	.gpu.pmic	= &tps659038,
-	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-	.core.value	= VDD_CORE_DRA7,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
-	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.core.addr	= TPS659038_REG_ADDR_SMPS7,
-	.core.pmic	= &tps659038,
-
-	.iva.value	= VDD_IVA_DRA7,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
-	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
-	.iva.pmic	= &tps659038,
-	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
-	.mpu.value	= VDD_MPU_DRA7,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
-	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
-	.mpu.pmic	= &tps659038,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-	.core.value	= VDD_CORE_DRA7,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
-	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.core.addr	= TPS65917_REG_ADDR_SMPS2,
-	.core.pmic	= &tps659038,
-
-	/*
-	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
-	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
-	 */
-	.gpu.value	= VDD_GPU_DRA7,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
-	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
-	.gpu.pmic	= &tps659038,
-	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
-	.eve.value	= VDD_EVE_DRA7,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
-	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
-	.eve.pmic	= &tps659038,
-	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
-	.iva.value	= VDD_IVA_DRA7,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
-	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
-	.iva.pmic	= &tps659038,
-	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -802,7 +726,6 @@ void __weak hw_data_init(void)
 	case DRA752_ES2_0:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
-	*omap_vcores = &dra752_volts;
 	*ctrl = &dra7xx_ctrl;
 	break;
 
@@ -810,7 +733,6 @@ void __weak hw_data_init(void)
 	case DRA722_ES2_0:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
-	*omap_vcores = &dra722_volts;
 	*ctrl = &dra7xx_ctrl;
 	break;