diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 61 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 20 |
2 files changed, 77 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 64514b1634..27a3f2f4e6 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -18,6 +18,8 @@ enum pll_clocks { PLL_BUS, /* System Bus PLL*/ PLL_USBOTG, /* OTG USB PLL */ PLL_ENET, /* ENET PLL */ + PLL_AUDIO, /* AUDIO PLL */ + PLL_VIDEO, /* AUDIO PLL */ }; struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -204,7 +206,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num) } static u32 decode_pll(enum pll_clocks pll, u32 infreq) { - u32 div; + u32 div, test_div, pll_num, pll_denom; switch (pll) { case PLL_SYS: @@ -227,6 +229,44 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) div &= BM_ANADIG_PLL_ENET_DIV_SELECT; return 25000000 * (div + (div >> 1) + 1); + case PLL_AUDIO: + div = __raw_readl(&imx_ccm->analog_pll_audio); + if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE)) + return 0; + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */ + if (div & BM_ANADIG_PLL_AUDIO_BYPASS) + return MXC_HCLK; + pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num); + pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom); + test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >> + BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT; + div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT; + if (test_div == 3) { + debug("Error test_div\n"); + return 0; + } + test_div = 1 << (2 - test_div); + + return infreq * (div + pll_num / pll_denom) / test_div; + case PLL_VIDEO: + div = __raw_readl(&imx_ccm->analog_pll_video); + if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE)) + return 0; + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */ + if (div & BM_ANADIG_PLL_VIDEO_BYPASS) + return MXC_HCLK; + pll_num = __raw_readl(&imx_ccm->analog_pll_video_num); + pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom); + test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >> + BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT; + if (test_div == 3) { + debug("Error test_div\n"); + return 0; + } + test_div = 1 << (2 - test_div); + + return infreq * (div + pll_num / pll_denom) / test_div; default: return 0; } @@ -437,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void) u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); - u32 freq, podf, per2_clk2_podf; + u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) { @@ -472,8 +512,21 @@ static u32 get_mmdc_ch0_clk(void) freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - /* static / 2 divider */ - freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; + pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); + switch (pmu_misc2_audio_div) { + case 0: + case 2: + pmu_misc2_audio_div = 1; + break; + case 1: + pmu_misc2_audio_div = 2; + break; + case 3: + pmu_misc2_audio_div = 4; + break; + } + freq = decode_pll(PLL_AUDIO, MXC_HCLK) / + pmu_misc2_audio_div; break; } } diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index c777922e9d..1d8e470971 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -130,6 +130,24 @@ static void init_csu(void) writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); } +static void imx_enet_mdio_fixup(void) +{ + struct iomuxc_gpr_base_regs *gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* + * The management data input/output (MDIO) requires open-drain, + * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports + * this feature. So to TO1.1, need to enable open drain by setting + * bits GPR0[8:7]. + */ + + if (soc_rev() >= CHIP_REV_1_1) { + setbits_le32(&gpr_regs->gpr[0], + IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + } +} + int arch_cpu_init(void) { init_aips(); @@ -138,6 +156,8 @@ int arch_cpu_init(void) /* Disable PDE bit of WMCR register */ imx_set_wdog_powerdown(false); + imx_enet_mdio_fixup(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); |