diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/Makefile | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/clock.c | 74 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/cpu.c | 176 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/lowlevel.S | 21 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/prcmu.c | 214 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/timer.c | 135 |
7 files changed, 0 insertions, 630 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 79a38df2cb..c8d142220a 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -52,5 +52,4 @@ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ -obj-$(CONFIG_U8500) += u8500/ obj-$(CONFIG_VF610) += vf610/ diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile deleted file mode 100644 index fad9d4ae3a..0000000000 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := timer.o clock.o prcmu.o cpu.o -obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c deleted file mode 100644 index 1e3b3d5205..0000000000 --- a/arch/arm/cpu/armv7/u8500/clock.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2009 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct clkrst { - unsigned int pcken; - unsigned int pckdis; - unsigned int kcken; - unsigned int kckdis; -}; - -static unsigned int clkrst_base[] = { - U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - 0, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE, - U8500_CLKRST7_BASE, /* ED only */ -}; - -/* Turn on peripheral clock at PRCC level */ -void u8500_clock_enable(int periph, int cluster, int kern) -{ - struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1]; - - if (kern != -1) - writel(1 << kern, &clkrst->kcken); - - if (cluster != -1) - writel(1 << cluster, &clkrst->pcken); -} - -void db8500_clocks_init(void) -{ - /* - * Enable all clocks. This is u-boot, we can enable it all. There is no - * powersave in u-boot. - */ - - u8500_clock_enable(1, 9, -1); /* GPIO0 */ - u8500_clock_enable(2, 11, -1);/* GPIO1 */ - u8500_clock_enable(3, 8, -1); /* GPIO2 */ - u8500_clock_enable(5, 1, -1); /* GPIO3 */ - u8500_clock_enable(3, 6, 6); /* UART2 */ - u8500_clock_enable(3, 3, 3); /* I2C0 */ - u8500_clock_enable(1, 5, 5); /* SDI0 */ - u8500_clock_enable(2, 4, 2); /* SDI4 */ - u8500_clock_enable(6, 6, -1); /* MTU0 */ - u8500_clock_enable(3, 4, 4); /* SDI2 */ - - /* - * Enabling clocks for all devices which are AMBA devices in the - * kernel. Otherwise they will not get probe()'d because the - * peripheral ID register will not be powered. - */ - - /* XXX: some of these differ between ED/V1 */ - - u8500_clock_enable(1, 1, 1); /* UART1 */ - u8500_clock_enable(1, 0, 0); /* UART0 */ - u8500_clock_enable(3, 2, 2); /* SSP1 */ - u8500_clock_enable(3, 1, 1); /* SSP0 */ - u8500_clock_enable(2, 8, -1); /* SPI0 */ - u8500_clock_enable(2, 5, 3); /* MSP2 */ -} diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c deleted file mode 100644 index d8634bebbd..0000000000 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2012 Linaro Limited - * Mathieu Poirier <mathieu.poirier@linaro.org> - * - * Based on original code from Joakim Axelsson at ST-Ericsson - * (C) Copyright 2010 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/prcmu.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> - -#include <asm/arch/hardware.h> - -#define CPUID_DB8500V1 0x411fc091 -#define CPUID_DB8500V2 0x412fc091 -#define ASICID_DB8500V11 0x008500A1 - -#define CACHE_CONTR_BASE 0xA0412000 -/* Cache controller register offsets - * as found in ARM's technical reference manual - */ -#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C) -#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900) -#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904) - -static unsigned int read_asicid(void); - -static inline unsigned int read_cpuid(void) -{ - unsigned int val; - - /* Main ID register (MIDR) */ - asm("mrc p15, 0, %0, c0, c0, 0" - : "=r" (val) - : - : "cc"); - - return val; -} - -static int cpu_is_u8500v11(void) -{ - return read_asicid() == ASICID_DB8500V11; -} - -static int cpu_is_u8500v2(void) -{ - return read_cpuid() == CPUID_DB8500V2; -} - -static unsigned int read_asicid(void) -{ - unsigned int *address; - - if (cpu_is_u8500v2()) - address = (void *) U8500_ASIC_ID_LOC_V2; - else - address = (void *) U8500_ASIC_ID_LOC_ED_V1; - - return readl(address); -} - -void cpu_cache_initialization(void) -{ - unsigned int value; - /* invalidate all cache entries */ - writel(0xFFFF, CACHE_INVAL_BY_WAY); - - /* ways are set to '0' when they are totally - * cleaned and invalidated - */ - do { - value = readl(CACHE_INVAL_BY_WAY); - } while (value & 0xFF); - - /* Invalidate register 9 D and I lockdown */ - writel(0xFF, CACHE_LOCKDOWN_BY_D); - writel(0xFF, CACHE_LOCKDOWN_BY_I); -} - -#ifdef CONFIG_ARCH_CPU_INIT -/* - * SOC specific cpu init - */ -int arch_cpu_init(void) -{ - db8500_prcmu_init(); - db8500_clocks_init(); - - return 0; -} -#endif /* CONFIG_ARCH_CPU_INIT */ - -#ifdef CONFIG_MMC - -int u8500_mmc_power_init(void) -{ - int ret; - int enable, voltage; - int ab8500_revision; - - if (!cpu_is_u8500v11() && !cpu_is_u8500v2()) - return 0; - - /* Get AB8500 revision */ - ret = ab8500_read(AB8500_MISC, AB8500_REV_REG); - if (ret < 0) - goto out; - - ab8500_revision = ret; - - /* - * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD - * card to work. This is done by enabling the regulators in the AB8500 - * via PRCMU I2C transactions. - * - * This code is derived from the handling of AB8500_LDO_VAUX3 in - * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. - * - * Turn off and delay is required to have it work across soft reboots. - */ - - /* Turn off (read-modify-write) */ - ret = ab8500_read(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG); - if (ret < 0) - goto out; - - enable = ret; - - /* Turn off */ - ret = ab8500_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, - enable & ~LDO_VAUX3_ENABLE_MASK); - if (ret < 0) - goto out; - - udelay(10 * 1000); - - /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */ - ret = ab8500_read(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG); - if (ret < 0) - goto out; - - voltage = ret; - - if (ab8500_revision < 0x20) { - voltage &= ~LDO_VAUX3_SEL_MASK; - voltage |= LDO_VAUX3_SEL_2V9; - } else { - voltage &= ~LDO_VAUX3_V2_SEL_MASK; - voltage |= LDO_VAUX3_V2_SEL_2V91; - } - - ret = ab8500_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, voltage); - if (ret < 0) - goto out; - - /* Turn on the supply */ - enable &= ~LDO_VAUX3_ENABLE_MASK; - enable |= LDO_VAUX3_ENABLE_VAL; - - ret = ab8500_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, enable); - -out: - return ret; -} -#endif /* CONFIG_MMC */ diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S deleted file mode 100644 index d3e3920601..0000000000 --- a/arch/arm/cpu/armv7/u8500/lowlevel.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2011 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> - -ENTRY(lowlevel_init) - mov pc, lr -ENDPROC(lowlevel_init) - - .align 5 -ENTRY(reset_cpu) - ldr r0, =CFG_PRCMU_BASE - ldr r1, =0x1 - str r1, [r0, #0x228] -_loop_forever: - b _loop_forever -ENDPROC(reset_cpu) diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c deleted file mode 100644 index 26ffdc2e02..0000000000 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Adapted from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * NOTE: This currently does not support the I2C workaround access method. - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/arch/prcmu.h> - -/* CPU mailbox registers */ -#define PRCMU_I2C_WRITE(slave) \ - (((slave) << 1) | I2CWRITE | (1 << 6)) -#define PRCMU_I2C_READ(slave) \ - (((slave) << 1) | I2CREAD | (1 << 6)) - -#define I2C_MBOX_BIT (1 << 5) - -static int prcmu_is_ready(void) -{ - int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; - if (!ready) - printf("PRCMU firmware not ready\n"); - return ready; -} - -static int wait_for_i2c_mbx_rdy(void) -{ - int timeout = 10000; - - if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) { - printf("prcmu: warning i2c mailbox was not acked\n"); - /* clear mailbox 5 ack irq */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); - } - - /* check any already on-going transaction */ - while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout) - timeout--; - - if (timeout == 0) - return -1; - - return 0; -} - -static int wait_for_i2c_req_done(void) -{ - int timeout = 10000; - - /* Set an interrupt to XP70 */ - writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET); - - /* wait for mailbox 5 (i2c) ack */ - while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout) - timeout--; - - if (timeout == 0) - return -1; - - return 0; -} - -/** - * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db8500 register to be accessed - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_read(u8 reg, u16 slave) -{ - uint8_t i2c_status; - uint8_t i2c_val; - int ret; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", - reg, slave); - - ret = wait_for_i2c_mbx_rdy(); - if (ret) { - printf("prcmu_i2c_read: mailbox became not ready\n"); - return ret; - } - - /* prepare the data for mailbox 5 */ - writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(0, PRCM_REQ_MB5_I2CVAL); - - ret = wait_for_i2c_req_done(); - if (ret) { - printf("prcmu_i2c_read: mailbox request timed out\n"); - return ret; - } - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - i2c_val = readb(PRCM_ACK_MB5_VAL); - /* clear mailbox 5 ack irq */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); - - if (i2c_status == I2C_RD_OK) - return i2c_val; - - printf("prcmu_i2c_read:read return status= %d\n", i2c_status); - return -1; -} - -/** - * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db800 register to be written to - * @reg_data: - the data to write - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) -{ - uint8_t i2c_status; - int ret; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", - reg, slave); - - ret = wait_for_i2c_mbx_rdy(); - if (ret) { - printf("prcmu_i2c_write: mailbox became not ready\n"); - return ret; - } - - /* prepare the data for mailbox 5 */ - writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(reg_data, PRCM_REQ_MB5_I2CVAL); - - ret = wait_for_i2c_req_done(); - if (ret) { - printf("prcmu_i2c_write: mailbox request timed out\n"); - return ret; - } - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - debug("\ni2c_status = %x\n", i2c_status); - /* clear mailbox 5 ack irq */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); - - if (i2c_status == I2C_WR_OK) - return 0; - - printf("%s: i2c_status : 0x%x\n", __func__, i2c_status); - return -1; -} - -void u8500_prcmu_enable(u32 *reg) -{ - writel(readl(reg) | (1 << 8), reg); -} - -void db8500_prcmu_init(void) -{ - /* Enable timers */ - writel(1 << 17, PRCM_TCR); - - u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); - /* PER4CLK does not exist */ - u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); - /* Only exists in ED but is always ok to write to */ - u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); - - u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); - - u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); - - /* Clean up the mailbox interrupts after pre-u-boot code. */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); -} diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c deleted file mode 100644 index 6b74e13d9c..0000000000 --- a/arch/arm/cpu/armv7/u8500/timer.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2010 Linaro Limited - * John Rigby <john.rigby@linaro.org> - * - * Based on original from Linux kernel source and - * internal ST-Ericsson U-Boot source. - * (C) Copyright 2009 Alessandro Rubini - * (C) Copyright 2010 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The MTU device has some interrupt control registers - * followed by 4 timers. - */ - -/* The timers */ -struct u8500_mtu_timer { - u32 lr; /* Load value */ - u32 cv; /* Current value */ - u32 cr; /* Control reg */ - u32 bglr; /* ??? */ -}; - -/* The MTU that contains the timers */ -struct u8500_mtu { - u32 imsc; /* Interrupt mask set/clear */ - u32 ris; /* Raw interrupt status */ - u32 mis; /* Masked interrupt status */ - u32 icr; /* Interrupt clear register */ - struct u8500_mtu_timer pt[4]; -}; - -/* bits for the control register */ -#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */ -#define MTU_CR_32BITS 0x02 - -#define MTU_CR_PRESCALE_1 0x00 -#define MTU_CR_PRESCALE_16 0x04 -#define MTU_CR_PRESCALE_256 0x08 -#define MTU_CR_PRESCALE_MASK 0x0c - -#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CR_ENA 0x80 - -/* - * The MTU is clocked at 133 MHz by default. (V1 and later) - */ -#define TIMER_CLOCK (133 * 1000 * 1000 / 16) -#define COUNT_TO_USEC(x) ((x) * 16 / 133) -#define USEC_TO_COUNT(x) ((x) * 133 / 16) -#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) -#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -#define TIMER_LOAD_VAL 0xffffffff - -/* - * MTU timer to use (from 0 to 3). - */ -#define MTU_TIMER 2 - -static struct u8500_mtu_timer *timer_base = - &((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER]; - -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(&timer_base->cv)) - -/* Configure a free-running, auto-wrap counter with /16 prescaler */ -int timer_init(void) -{ - writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS, - &timer_base->cr); - return 0; -} - -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = TICKS_TO_HZ(READ_TIMER()); - - if (now >= gd->arch.lastinc) { /* normal (non rollover) */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { /* rollover */ - gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* Delay x useconds */ -void __udelay(ulong usec) -{ - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - ulong now, last = READ_TIMER(); - - while (tmo > 0) { - now = READ_TIMER(); - if (now > last) /* normal (non rollover) */ - tmo -= now - last; - else /* rollover */ - tmo -= TIMER_LOAD_VAL - last + now; - last = now; - } -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * Emulation of Power architecture long long timebase. - * - * TODO: Support gd->arch.tbu for real long long timebase. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * Emulation of Power architecture timebase. - * NB: Low resolution compared to Power tbclk. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} |