diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx51/timer.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/timer.c | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/board.c | 11 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/mem.c | 45 |
5 files changed, 58 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c index 81c4a06143..110edbfa85 100644 --- a/arch/arm/cpu/armv7/mx51/timer.c +++ b/arch/arm/cpu/armv7/mx51/timer.c @@ -89,7 +89,7 @@ ulong get_timer_masked(void) timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ)) - lastinc) + val; lastinc = val; - return val; + return timestamp; } ulong get_timer(ulong base) diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 69e285ff1d..6b8cf7ba2d 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -41,12 +41,8 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; /* * Nothing really to do with interrupts, just starts up a counter. - * We run the counter with 13MHz, divided by 8, resulting in timer - * frequency of 1.625MHz. With 32bit counter register, counter - * overflows in ~44min */ -/* 13MHz / 8 = 1.625MHz */ #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) #define TIMER_LOAD_VAL 0xffffffff @@ -84,11 +80,6 @@ void set_timer(ulong t) /* delay x useconds */ void __udelay(unsigned long usec) { -#if defined(CONFIG_OMAP44XX) - /* TODO temporary hack until OMAP4 clock setup routines are present */ - if (usec > 1000) - usec = usec/1000; -#endif long tmo = usec * (TIMER_CLOCK / 1000) / 1000; unsigned long now, last = readl(&timer_base->tcrr); diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index ecf64f999b..d926fbb480 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a SOBJS += lowlevel_init.o COBJS += board.o +COBJS += mem.o COBJS += sys_info.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 5bf717303d..2e80d1fbf7 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -88,3 +88,14 @@ int checkboard(void) return 0; } +/* +* This function is called by start_armboot. You can reliably use static +* data. Any boot-time function that require static data should be +* called from here +*/ +int arch_cpu_init(void) +{ + set_muxconf_regs(); + return 0; +} + diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap4/mem.c new file mode 100644 index 0000000000..878f0e3042 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/mem.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Steve Sakoman <steve@sakoman.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> + +struct gpmc *gpmc_cfg; + +/***************************************************** + * gpmc_init(): init gpmc bus + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + gpmc_cfg = (struct gpmc *)GPMC_BASE; + + /* global settings */ + writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ + writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ + + /* + * Disable the GPMC0 config set by ROM code + * It conflicts with our MPDB (both at 0x08000000) + */ + writel(0, &gpmc_cfg->cs[0].config7); +} |