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-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c2
-rw-r--r--arch/arm/cpu/armv8/start.S2
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d580a43b41..a9b12a43ad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num)
/*
* DDR controller 0 & 1 are on memory complex 0
- * DDR controler 2 is on memory complext 1
+ * DDR controller 2 is on memory complext 1
*/
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num >= 2)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index deb44a895f..c3cc8199ca 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -214,7 +214,9 @@ WEAK(lowlevel_init)
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
#endif
+#endif
+#ifndef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, 2f
/*