diff options
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 24 |
7 files changed, 62 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 6c03dfb1d5..cefbdfe855 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,6 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH2 select SYS_FSL_DDR_BE select SYS_FSL_MMDC @@ -16,6 +17,7 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH2 select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -68,6 +70,7 @@ config ARCH_LS1046A config ARCH_LS1088A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH3 select SYS_FSL_DDR select SYS_FSL_DDR_LE @@ -493,8 +496,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A - default 0x70000000 if ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 115c3fc1d1..0cb6d4eb4d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,8 +7,10 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o +endif obj-$(CONFIG_SPL) += spl.o obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 00d2564c79..1e0030cbfb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -30,6 +30,7 @@ #endif #include <asm/arch/clock.h> #include <hwconfig.h> +#include <fsl_qbman.h> DECLARE_GLOBAL_DATA_PTR; @@ -565,6 +566,9 @@ int arch_early_init_r(void) #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_qbman_portals(); +#endif return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 39ffe1ab4d..80af318822 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -26,6 +26,8 @@ #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif +#include <asm/arch/speed.h> +#include <fsl_qbman.h> int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -442,6 +444,13 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_esdhc(blob, bd); #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + fdt_fixup_bportals(blob); + fdt_fixup_qportals(blob); + do_fixup_by_compat_u32(blob, "fsl,qman", + "clock-frequency", get_qman_freq(), 1); +#endif + #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 2d7775e54f..5f23aadc2c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -155,8 +155,22 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_localbus = sys_info->freq_systembus / CONFIG_SYS_FSL_IFC_CLK_DIV; #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + sys_info->freq_qman = sys_info->freq_systembus; +#endif } +#ifdef CONFIG_SYS_DPAA_QBMAN +unsigned long get_qman_freq(void) +{ + struct sys_info sys_info; + + get_sys_info(&sys_info); + + return sys_info.freq_qman; +} +#endif + int get_clocks(void) { struct sys_info sys_info; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ae57c0e31d..dc4a437344 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -341,6 +341,8 @@ int sata_init(void) #ifdef CONFIG_SYS_SATA2 ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); #endif @@ -348,6 +350,8 @@ int sata_init(void) #ifdef CONFIG_SYS_SATA1 ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); @@ -368,6 +372,8 @@ int sata_init(void) /* Disable SATA ECC */ out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 03e744e4a6..f385ed40e1 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -196,7 +196,10 @@ reset_sctrl: WEAK(apply_core_errata) mov x29, lr /* Save LR */ - /* For now, we support Cortex-A57 specific errata only */ + /* For now, we support Cortex-A53, Cortex-A57 specific errata */ + + /* Check if we are running on a Cortex-A53 core */ + branch_if_a53_core x0, apply_a53_core_errata /* Check if we are running on a Cortex-A57 core */ branch_if_a57_core x0, apply_a57_core_errata @@ -204,6 +207,25 @@ WEAK(apply_core_errata) mov lr, x29 /* Restore LR */ ret +apply_a53_core_errata: + +#ifdef CONFIG_ARM_ERRATA_855873 + mrs x0, midr_el1 + tst x0, #(0xf << 20) + b.ne 0b + + mrs x0, midr_el1 + and x0, x0, #0xf + cmp x0, #3 + b.lt 0b + + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Enable data cache clean as data cache clean/invalidate */ + orr x0, x0, #1 << 44 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + b 0b + apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 |