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-rw-r--r--arch/arm/cpu/tegra124-common/Makefile11
-rw-r--r--arch/arm/cpu/tegra124-common/clock.c935
-rw-r--r--arch/arm/cpu/tegra124-common/funcmux.c71
-rw-r--r--arch/arm/cpu/tegra124-common/pinmux.c306
-rw-r--r--arch/arm/cpu/tegra124-common/xusb-padctl.c716
5 files changed, 0 insertions, 2039 deletions
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
deleted file mode 100644
index 7b59fb1216..0000000000
--- a/arch/arm/cpu/tegra124-common/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += clock.o
-obj-y += funcmux.o
-obj-y += pinmux.o
-obj-y += xusb-padctl.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
deleted file mode 100644
index fc8bd194dd..0000000000
--- a/arch/arm/cpu/tegra124-common/clock.c
+++ /dev/null
@@ -1,935 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra124 Clock control functions */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctr.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
-
-/*
- * Clock types that we can use as a source. The Tegra124 has muxes for the
- * peripheral clocks, and in most cases there are four options for the clock
- * source. This gives us a clock 'type' and exploits what commonality exists
- * in the device.
- *
- * Letters are obvious, except for T which means CLK_M, and S which means the
- * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
- * datasheet) and PLL_M are different things. The former is the basic
- * clock supplied to the SOC from an external oscillator. The latter is the
- * memory clock PLL.
- *
- * See definitions in clock_id in the header file.
- */
-enum clock_type_id {
- CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
- CLOCK_TYPE_MCPA, /* and so on */
- CLOCK_TYPE_MCPT,
- CLOCK_TYPE_PCM,
- CLOCK_TYPE_PCMT,
- CLOCK_TYPE_PDCT,
- CLOCK_TYPE_ACPT,
- CLOCK_TYPE_ASPTE,
- CLOCK_TYPE_PMDACD2T,
- CLOCK_TYPE_PCST,
-
- CLOCK_TYPE_PC2CC3M,
- CLOCK_TYPE_PC2CC3S_T,
- CLOCK_TYPE_PC2CC3M_T,
- CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
- CLOCK_TYPE_MC2CC3P_A,
- CLOCK_TYPE_M,
- CLOCK_TYPE_MCPTM2C2C3,
- CLOCK_TYPE_PC2CC3T_S,
- CLOCK_TYPE_AC2CC3P_TS2,
-
- CLOCK_TYPE_COUNT,
- CLOCK_TYPE_NONE = -1, /* invalid clock type */
-};
-
-enum {
- CLOCK_MAX_MUX = 8 /* number of source options for each clock */
-};
-
-/*
- * Clock source mux for each clock type. This just converts our enum into
- * a list of mux sources for use by the code.
- *
- * Note:
- * The extra column in each clock source array is used to store the mask
- * bits in its register for the source.
- */
-#define CLK(x) CLOCK_ID_ ## x
-static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
- CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
- CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_28},
-
- /* Additional clock types on Tegra114+ */
- /* CLOCK_TYPE_PC2CC3M */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3S_T */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3M_T */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_MC2CC3P_A */
- { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_M */
- { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- /* CLOCK_TYPE_MCPTM2C2C3 */
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3T_S */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_AC2CC3P_TS2 */
- { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
- MASK_BITS_31_29},
-};
-
-/*
- * Clock type for each peripheral clock source. We put the name in each
- * record just so it is easy to match things up
- */
-#define TYPE(name, type) type
-static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
- /* 0x00 */
- TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
- TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
- TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x08 */
- TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
-
- /* 0x10 */
- TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
-
- /* 0x18 */
- TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x20 */
- TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
-
- /* 0x28 */
- TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x30 */
- TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
-
- /* 0x38 */
- TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
-
- /* 0x40 */
- TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
- TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
- TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x48 */
- TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
- TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
-
- /* 0x50 */
- TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
- TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
-
- /* 0x58 */
- TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
-
- /* 0x60 */
- TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
-
- /* 0x68 */
- TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
-
- /* 0x70 */
- TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
-
- /* 0x78 */
- TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
- TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
-};
-
-/*
- * This array translates a periph_id to a periphc_internal_id
- *
- * Not present/matched up:
- * uint vi_sensor; _VI_SENSOR_0, 0x1A8
- * SPDIF - which is both 0x08 and 0x0c
- *
- */
-#define NONE(name) (-1)
-#define OFFSET(name, value) PERIPHC_ ## name
-static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
- /* Low word: 31:0 */
- NONE(CPU),
- NONE(COP),
- NONE(TRIGSYS),
- NONE(ISPB),
- NONE(RESERVED4),
- NONE(TMR),
- PERIPHC_UART1,
- PERIPHC_UART2, /* and vfir 0x68 */
-
- /* 8 */
- NONE(GPIO),
- PERIPHC_SDMMC2,
- PERIPHC_SPDIF_IN,
- PERIPHC_I2S1,
- PERIPHC_I2C1,
- NONE(RESERVED13),
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC4,
-
- /* 16 */
- NONE(TCW),
- PERIPHC_PWM,
- PERIPHC_I2S2,
- NONE(RESERVED19),
- PERIPHC_VI,
- NONE(RESERVED21),
- NONE(USBD),
- NONE(ISP),
-
- /* 24 */
- NONE(RESERVED24),
- NONE(RESERVED25),
- PERIPHC_DISP2,
- PERIPHC_DISP1,
- PERIPHC_HOST1X,
- NONE(VCP),
- PERIPHC_I2S0,
- NONE(CACHE2),
-
- /* Middle word: 63:32 */
- NONE(MEM),
- NONE(AHBDMA),
- NONE(APBDMA),
- NONE(RESERVED35),
- NONE(RESERVED36),
- NONE(STAT_MON),
- NONE(RESERVED38),
- NONE(FUSE),
-
- /* 40 */
- NONE(KFUSE),
- PERIPHC_SBC1, /* SBCx = SPIx */
- PERIPHC_NOR,
- NONE(RESERVED43),
- PERIPHC_SBC2,
- NONE(XIO),
- PERIPHC_SBC3,
- PERIPHC_I2C5,
-
- /* 48 */
- NONE(DSI),
- NONE(RESERVED49),
- PERIPHC_HSI,
- PERIPHC_HDMI,
- NONE(CSI),
- NONE(RESERVED53),
- PERIPHC_I2C2,
- PERIPHC_UART3,
-
- /* 56 */
- NONE(MIPI_CAL),
- PERIPHC_EMC,
- NONE(USB2),
- NONE(USB3),
- NONE(RESERVED60),
- PERIPHC_VDE,
- NONE(BSEA),
- NONE(BSEV),
-
- /* Upper word 95:64 */
- NONE(RESERVED64),
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_I2C3,
- PERIPHC_SBC4,
- PERIPHC_SDMMC3,
- NONE(PCIE),
- PERIPHC_OWR,
-
- /* 72 */
- NONE(AFI),
- PERIPHC_CSITE,
- NONE(PCIEXCLK),
- NONE(AVPUCQ),
- NONE(LA),
- NONE(TRACECLKIN),
- NONE(SOC_THERM),
- NONE(DTV),
-
- /* 80 */
- NONE(RESERVED80),
- PERIPHC_I2CSLOW,
- NONE(DSIB),
- PERIPHC_TSEC,
- NONE(RESERVED84),
- NONE(RESERVED85),
- NONE(RESERVED86),
- NONE(EMUCIF),
-
- /* 88 */
- NONE(RESERVED88),
- NONE(XUSB_HOST),
- NONE(RESERVED90),
- PERIPHC_MSENC,
- NONE(RESERVED92),
- NONE(RESERVED93),
- NONE(RESERVED94),
- NONE(XUSB_DEV),
-
- /* V word: 31:0 */
- NONE(CPUG),
- NONE(CPULP),
- NONE(V_RESERVED2),
- PERIPHC_MSELECT,
- NONE(V_RESERVED4),
- PERIPHC_I2S3,
- PERIPHC_I2S4,
- PERIPHC_I2C4,
-
- /* 104 */
- PERIPHC_SBC5,
- PERIPHC_SBC6,
- PERIPHC_AUDIO,
- NONE(APBIF),
- PERIPHC_DAM0,
- PERIPHC_DAM1,
- PERIPHC_DAM2,
- PERIPHC_HDA2CODEC2X,
-
- /* 112 */
- NONE(ATOMICS),
- NONE(V_RESERVED17),
- NONE(V_RESERVED18),
- NONE(V_RESERVED19),
- NONE(V_RESERVED20),
- NONE(V_RESERVED21),
- NONE(V_RESERVED22),
- PERIPHC_ACTMON,
-
- /* 120 */
- NONE(EXTPERIPH1),
- NONE(EXTPERIPH2),
- NONE(EXTPERIPH3),
- NONE(OOB),
- PERIPHC_SATA,
- PERIPHC_HDA,
- NONE(TZRAM),
- NONE(SE),
-
- /* W word: 31:0 */
- NONE(HDA2HDMICODEC),
- NONE(SATACOLD),
- NONE(W_RESERVED2),
- NONE(W_RESERVED3),
- NONE(W_RESERVED4),
- NONE(W_RESERVED5),
- NONE(W_RESERVED6),
- NONE(W_RESERVED7),
-
- /* 136 */
- NONE(CEC),
- NONE(W_RESERVED9),
- NONE(W_RESERVED10),
- NONE(W_RESERVED11),
- NONE(W_RESERVED12),
- NONE(W_RESERVED13),
- NONE(XUSB_PADCTL),
- NONE(W_RESERVED15),
-
- /* 144 */
- NONE(W_RESERVED16),
- NONE(W_RESERVED17),
- NONE(W_RESERVED18),
- NONE(W_RESERVED19),
- NONE(W_RESERVED20),
- NONE(ENTROPY),
- NONE(DDS),
- NONE(W_RESERVED23),
-
- /* 152 */
- NONE(DP2),
- NONE(AMX0),
- NONE(ADX0),
- NONE(DVFS),
- NONE(XUSB_SS),
- NONE(W_RESERVED29),
- NONE(W_RESERVED30),
- NONE(W_RESERVED31),
-
- /* X word: 31:0 */
- NONE(SPARE),
- NONE(X_RESERVED1),
- NONE(X_RESERVED2),
- NONE(X_RESERVED3),
- NONE(CAM_MCLK),
- NONE(CAM_MCLK2),
- PERIPHC_I2C6,
- NONE(X_RESERVED7),
-
- /* 168 */
- NONE(X_RESERVED8),
- NONE(X_RESERVED9),
- NONE(X_RESERVED10),
- NONE(VIM2_CLK),
- NONE(X_RESERVED12),
- NONE(X_RESERVED13),
- NONE(EMC_DLL),
- NONE(X_RESERVED15),
-
- /* 176 */
- NONE(HDMI_AUDIO),
- NONE(CLK72MHZ),
- NONE(VIC),
- NONE(X_RESERVED19),
- NONE(ADX1),
- NONE(DPAUX),
- NONE(SOR0),
- NONE(X_RESERVED23),
-
- /* 184 */
- NONE(GPU),
- NONE(AMX1),
- NONE(X_RESERVED26),
- NONE(X_RESERVED27),
- NONE(X_RESERVED28),
- NONE(X_RESERVED29),
- NONE(X_RESERVED30),
- NONE(X_RESERVED31),
-};
-
-/*
- * Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that Tegra30+ support 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
- */
-enum clock_osc_freq clock_get_osc_freq(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
-}
-
-/* Returns a pointer to the clock source register for a peripheral */
-u32 *get_periph_source_reg(enum periph_id periph_id)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- enum periphc_internal_id internal_id;
-
- /* Coresight is a special case */
- if (periph_id == PERIPH_ID_CSI)
- return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
-
- assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
- internal_id = periph_id_to_internal_id[periph_id];
- assert(internal_id != -1);
- if (internal_id >= PERIPHC_VW_FIRST) {
- internal_id -= PERIPHC_VW_FIRST;
- return &clkrst->crc_clk_src_vw[internal_id];
- } else {
- return &clkrst->crc_clk_src[internal_id];
- }
-}
-
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id peripheral to start
- * @param source PLL id of required parent clock
- * @param mux_bits Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
- enum clock_id parent, int *mux_bits, int *divider_bits)
-{
- enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
-
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PC2CC3M_T16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
-
- for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
- if (clock_source[type][mux] == parent)
- return mux;
-
- /* if we get here, either us or the caller has made a mistake */
- printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
- parent);
- return -1;
-}
-
-void clock_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *clk;
- u32 reg;
-
- /* Enable/disable the clock to this peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
- clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
- else
- clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
- reg = readl(clk);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, clk);
-}
-
-void reset_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *reset;
- u32 reg;
-
- /* Enable/disable reset to the peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if (periph_id < PERIPH_ID_VW_FIRST)
- reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
- else
- reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
- reg = readl(reset);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, reset);
-}
-
-#ifdef CONFIG_OF_CONTROL
-/*
- * Convert a device tree clock ID to our peripheral ID. They are mostly
- * the same but we are very cautious so we check that a valid clock ID is
- * provided.
- *
- * @param clk_id Clock ID according to tegra124 device tree binding
- * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
- */
-enum periph_id clk_id_to_periph_id(int clk_id)
-{
- if (clk_id > PERIPH_ID_COUNT)
- return PERIPH_ID_NONE;
-
- switch (clk_id) {
- case PERIPH_ID_RESERVED4:
- case PERIPH_ID_RESERVED25:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED36:
- case PERIPH_ID_RESERVED38:
- case PERIPH_ID_RESERVED43:
- case PERIPH_ID_RESERVED49:
- case PERIPH_ID_RESERVED53:
- case PERIPH_ID_RESERVED64:
- case PERIPH_ID_RESERVED84:
- case PERIPH_ID_RESERVED85:
- case PERIPH_ID_RESERVED86:
- case PERIPH_ID_RESERVED88:
- case PERIPH_ID_RESERVED90:
- case PERIPH_ID_RESERVED92:
- case PERIPH_ID_RESERVED93:
- case PERIPH_ID_RESERVED94:
- case PERIPH_ID_V_RESERVED2:
- case PERIPH_ID_V_RESERVED4:
- case PERIPH_ID_V_RESERVED17:
- case PERIPH_ID_V_RESERVED18:
- case PERIPH_ID_V_RESERVED19:
- case PERIPH_ID_V_RESERVED20:
- case PERIPH_ID_V_RESERVED21:
- case PERIPH_ID_V_RESERVED22:
- case PERIPH_ID_W_RESERVED2:
- case PERIPH_ID_W_RESERVED3:
- case PERIPH_ID_W_RESERVED4:
- case PERIPH_ID_W_RESERVED5:
- case PERIPH_ID_W_RESERVED6:
- case PERIPH_ID_W_RESERVED7:
- case PERIPH_ID_W_RESERVED9:
- case PERIPH_ID_W_RESERVED10:
- case PERIPH_ID_W_RESERVED11:
- case PERIPH_ID_W_RESERVED12:
- case PERIPH_ID_W_RESERVED13:
- case PERIPH_ID_W_RESERVED15:
- case PERIPH_ID_W_RESERVED16:
- case PERIPH_ID_W_RESERVED17:
- case PERIPH_ID_W_RESERVED18:
- case PERIPH_ID_W_RESERVED19:
- case PERIPH_ID_W_RESERVED20:
- case PERIPH_ID_W_RESERVED23:
- case PERIPH_ID_W_RESERVED29:
- case PERIPH_ID_W_RESERVED30:
- case PERIPH_ID_W_RESERVED31:
- return PERIPH_ID_NONE;
- default:
- return clk_id;
- }
-}
-#endif /* CONFIG_OF_CONTROL */
-
-void clock_early_init(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-
- tegra30_set_up_pllp();
-
- /*
- * PLLC output frequency set to 600Mhz
- * PLLD output frequency set to 925Mhz
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
-
- /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
- writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
-
- /* PLLC_MISC: Set LOCK_ENABLE */
- writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
- udelay(2);
-
- /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
- writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
- udelay(2);
-}
-
-void arch_timer_init(void)
-{
- struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
- u32 freq, val;
-
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
-
- /* ARM CNTFRQ */
- asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
-
- /* Only Tegra114+ has the System Counter regs */
- debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
- writel(freq, &sysctr->cntfid0);
-
- val = readl(&sysctr->cntcr);
- val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
- writel(val, &sysctr->cntcr);
- debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
-}
-
-#define PLLE_SS_CNTL 0x68
-#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
-#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
-#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
-#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
-#define PLLE_SS_CNTL_SSCBYP (1 << 12)
-#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
-#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
-#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
-
-#define PLLE_BASE 0x0e8
-#define PLLE_BASE_ENABLE (1 << 30)
-#define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
-#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
-#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
-#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
-
-#define PLLE_MISC 0x0ec
-#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
-#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
-#define PLLE_MISC_LOCK_ENABLE (1 << 9)
-#define PLLE_MISC_PTS (1 << 8)
-#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
-#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
-
-#define PLLE_AUX 0x48c
-#define PLLE_AUX_SEQ_ENABLE (1 << 24)
-#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
-
-int tegra_plle_enable(void)
-{
- unsigned int m = 1, n = 200, cpcon = 13;
- u32 value;
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value &= ~PLLE_BASE_LOCK_OVERRIDE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
- value |= PLLE_AUX_ENABLE_SWCTL;
- value &= ~PLLE_AUX_SEQ_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value |= PLLE_MISC_IDDQ_SWCTL;
- value &= ~PLLE_MISC_IDDQ_OVERRIDE;
- value |= PLLE_MISC_LOCK_ENABLE;
- value |= PLLE_MISC_PTS;
- value |= PLLE_MISC_VREG_BG_CTRL(3);
- value |= PLLE_MISC_VREG_CTRL(2);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- udelay(5);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
- PLLE_SS_CNTL_BYPASS_SS;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value &= ~PLLE_BASE_PLDIV_CML(0xf);
- value &= ~PLLE_BASE_NDIV(0xff);
- value &= ~PLLE_BASE_MDIV(0xff);
- value |= PLLE_BASE_PLDIV_CML(cpcon);
- value |= PLLE_BASE_NDIV(n);
- value |= PLLE_BASE_MDIV(m);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value |= PLLE_BASE_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- /* wait for lock */
- udelay(300);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_SSCINVERT;
- value &= ~PLLE_SS_CNTL_SSCCENTER;
-
- value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
- value &= ~PLLE_SS_CNTL_SSCINC(0xff);
- value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
-
- value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
- value |= PLLE_SS_CNTL_SSCINC(0x01);
- value |= PLLE_SS_CNTL_SSCMAX(0x25);
-
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_SSCBYP;
- value &= ~PLLE_SS_CNTL_BYPASS_SS;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_INTERP_RESET;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- udelay(1);
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
deleted file mode 100644
index cced787e6b..0000000000
--- a/arch/arm/cpu/tegra124-common/funcmux.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra124 high-level function multiplexing */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART4:
- switch (config) {
- case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
- pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
-
- pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_PJ7);
- pinmux_tristate_disable(PMUX_PINGRP_PB0);
- pinmux_tristate_disable(PMUX_PINGRP_PB1);
- pinmux_tristate_disable(PMUX_PINGRP_PK7);
- break;
- }
- break;
-
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_KBC:
- pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
- PMUX_FUNC_UARTA);
-
- pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
- pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
deleted file mode 100644
index c6685eaae1..0000000000
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra124_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4),
- PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB),
- PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3068 */
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3110 */
- PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3164 */
- PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4),
- PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI),
- PIN(PU0, OWR, UARTA, GMI, RSVD4),
- PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU3, PWM0, UARTA, GMI, DISPLAYB),
- PIN(PU4, PWM1, UARTA, GMI, DISPLAYB),
- PIN(PU5, PWM2, UARTA, GMI, DISPLAYB),
- PIN(PU6, PWM3, UARTA, RSVD3, GMI),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT),
- PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PI7, RSVD1, TRACE, GMI, DTV),
- PIN(PK0, RSVD1, SDMMC3, GMI, SOC),
- PIN(PK1, SDMMC2, TRACE, GMI, RSVD4),
- PIN(PJ0, RSVD1, RSVD2, GMI, USB),
- PIN(PJ2, RSVD1, RSVD2, GMI, SOC),
- PIN(PK3, SDMMC2, TRACE, GMI, CCLA),
- PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT),
- PIN(PK2, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI3, RSVD1, RSVD2, GMI, SPI4),
- PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2),
- PIN(PG0, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PG1, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PG2, RSVD1, TRACE, GMI, RSVD4),
- PIN(PG3, RSVD1, TRACE, GMI, RSVD4),
- PIN(PG4, RSVD1, TMDS, GMI, SPI4),
- PIN(PG5, RSVD1, RSVD2, GMI, SPI4),
- PIN(PG6, RSVD1, RSVD2, GMI, SPI4),
- PIN(PG7, RSVD1, RSVD2, GMI, SPI4),
- PIN(PH0, PWM0, TRACE, GMI, DTV),
- PIN(PH1, PWM1, TMDS, GMI, DISPLAYA),
- PIN(PH2, PWM2, TMDS, GMI, CLDVFS),
- PIN(PH3, PWM3, SPI4, GMI, CLDVFS),
- PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PH6, SDMMC2, TRACE, GMI, DTV),
- PIN(PH7, SDMMC2, TRACE, GMI, DTV),
- PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT),
- PIN(PB0, UARTD, RSVD2, GMI, RSVD4),
- PIN(PB1, UARTD, RSVD2, GMI, RSVD4),
- PIN(PK7, UARTD, RSVD2, GMI, RSVD4),
- PIN(PI0, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI1, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI2, SDMMC2, TRACE, GMI, RSVD4),
- PIN(PI4, SPI4, TRACE, GMI, DISPLAYA),
- PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4),
- PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3284 */
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2),
- PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2),
- PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2),
- PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2),
- PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2),
- PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2),
- PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2),
- PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB),
- PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
- PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA),
- PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA),
- PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4),
- PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
- PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
- PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4),
- PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD),
- PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD),
- PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3324 */
- PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
- PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4),
- PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3),
- PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4),
- PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4),
- PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4),
- PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4),
- PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4),
- PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2),
- PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4),
- PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI),
- PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3390 */
- PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
- PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
- PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
- PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33bc */
- PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4),
- PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4),
- PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- /* Offset 0x33cc */
- PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4),
- PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33e0 */
- PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
- PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
- PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
- PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
- PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
- PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
- PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC),
- PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC),
- PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4),
- PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3430 */
- PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
diff --git a/arch/arm/cpu/tegra124-common/xusb-padctl.c b/arch/arm/cpu/tegra124-common/xusb-padctl.c
deleted file mode 100644
index 43af883f2c..0000000000
--- a/arch/arm/cpu/tegra124-common/xusb-padctl.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
-
-#include <common.h>
-#include <errno.h>
-#include <fdtdec.h>
-#include <malloc.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/xusb-padctl.h>
-
-#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
-
-#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
-
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
-
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
-
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
-
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
-
-enum tegra124_function {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
- TEGRA124_FUNC_UART,
- TEGRA124_FUNC_PCIE,
- TEGRA124_FUNC_USB3,
- TEGRA124_FUNC_SATA,
- TEGRA124_FUNC_RSVD,
-};
-
-static const char *const tegra124_functions[] = {
- "snps",
- "xusb",
- "uart",
- "pcie",
- "usb3",
- "sata",
- "rsvd",
-};
-
-static const unsigned int tegra124_otg_functions[] = {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
- TEGRA124_FUNC_UART,
- TEGRA124_FUNC_RSVD,
-};
-
-static const unsigned int tegra124_usb_functions[] = {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
-};
-
-static const unsigned int tegra124_pci_functions[] = {
- TEGRA124_FUNC_PCIE,
- TEGRA124_FUNC_USB3,
- TEGRA124_FUNC_SATA,
- TEGRA124_FUNC_RSVD,
-};
-
-struct tegra_xusb_padctl_lane {
- const char *name;
-
- unsigned int offset;
- unsigned int shift;
- unsigned int mask;
- unsigned int iddq;
-
- const unsigned int *funcs;
- unsigned int num_funcs;
-};
-
-#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
- { \
- .name = _name, \
- .offset = _offset, \
- .shift = _shift, \
- .mask = _mask, \
- .iddq = _iddq, \
- .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
- .funcs = tegra124_##_funcs##_functions, \
- }
-
-static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
- TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
- TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
- TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
- TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
- TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
- TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
- TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
- TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
- TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
- TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
- TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
- TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
-};
-
-struct tegra_xusb_phy_ops {
- int (*prepare)(struct tegra_xusb_phy *phy);
- int (*enable)(struct tegra_xusb_phy *phy);
- int (*disable)(struct tegra_xusb_phy *phy);
- int (*unprepare)(struct tegra_xusb_phy *phy);
-};
-
-struct tegra_xusb_phy {
- const struct tegra_xusb_phy_ops *ops;
-
- struct tegra_xusb_padctl *padctl;
-};
-
-struct tegra_xusb_padctl_pin {
- const struct tegra_xusb_padctl_lane *lane;
-
- unsigned int func;
- int iddq;
-};
-
-#define MAX_GROUPS 3
-#define MAX_PINS 6
-
-struct tegra_xusb_padctl_group {
- const char *name;
-
- const char *pins[MAX_PINS];
- unsigned int num_pins;
-
- const char *func;
- int iddq;
-};
-
-struct tegra_xusb_padctl_config {
- const char *name;
-
- struct tegra_xusb_padctl_group groups[MAX_GROUPS];
- unsigned int num_groups;
-};
-
-struct tegra_xusb_padctl {
- struct fdt_resource regs;
-
- unsigned int enable;
-
- struct tegra_xusb_phy phys[2];
-
- const struct tegra_xusb_padctl_lane *lanes;
- unsigned int num_lanes;
-
- const char *const *functions;
- unsigned int num_functions;
-
- struct tegra_xusb_padctl_config config;
-};
-
-static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
- unsigned long offset)
-{
- return readl(padctl->regs.start + offset);
-}
-
-static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
- u32 value, unsigned long offset)
-{
- writel(value, padctl->regs.start + offset);
-}
-
-static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
-{
- u32 value;
-
- if (padctl->enable++ > 0)
- return 0;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- return 0;
-}
-
-static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
-{
- u32 value;
-
- if (padctl->enable == 0) {
- error("tegra-xusb-padctl: unbalanced enable/disable");
- return 0;
- }
-
- if (--padctl->enable > 0)
- return 0;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- return 0;
-}
-
-static int phy_prepare(struct tegra_xusb_phy *phy)
-{
- return tegra_xusb_padctl_enable(phy->padctl);
-}
-
-static int phy_unprepare(struct tegra_xusb_phy *phy)
-{
- return tegra_xusb_padctl_disable(phy->padctl);
-}
-
-static int pcie_phy_enable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- int err = -ETIMEDOUT;
- unsigned long start;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
- value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
- XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
- XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- start = get_timer(0);
-
- while (get_timer(start) < 50) {
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
- err = 0;
- break;
- }
- }
-
- return err;
-}
-
-static int pcie_phy_disable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- return 0;
-}
-
-static int sata_phy_enable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- int err = -ETIMEDOUT;
- unsigned long start;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
- value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- start = get_timer(0);
-
- while (get_timer(start) < 50) {
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
- err = 0;
- break;
- }
- }
-
- return err;
-}
-
-static int sata_phy_disable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
- value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
- value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
-
- return 0;
-}
-
-static const struct tegra_xusb_phy_ops pcie_phy_ops = {
- .prepare = phy_prepare,
- .enable = pcie_phy_enable,
- .disable = pcie_phy_disable,
- .unprepare = phy_unprepare,
-};
-
-static const struct tegra_xusb_phy_ops sata_phy_ops = {
- .prepare = phy_prepare,
- .enable = sata_phy_enable,
- .disable = sata_phy_disable,
- .unprepare = phy_unprepare,
-};
-
-static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
- .phys = {
- [0] = {
- .ops = &pcie_phy_ops,
- },
- [1] = {
- .ops = &sata_phy_ops,
- },
- },
-};
-
-static const struct tegra_xusb_padctl_lane *
-tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
-{
- unsigned int i;
-
- for (i = 0; i < padctl->num_lanes; i++)
- if (strcmp(name, padctl->lanes[i].name) == 0)
- return &padctl->lanes[i];
-
- return NULL;
-}
-
-static int
-tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
- struct tegra_xusb_padctl_group *group,
- const void *fdt, int node)
-{
- unsigned int i;
- int len, err;
-
- group->name = fdt_get_name(fdt, node, &len);
-
- len = fdt_count_strings(fdt, node, "nvidia,lanes");
- if (len < 0) {
- error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property");
- return -EINVAL;
- }
-
- group->num_pins = len;
-
- for (i = 0; i < group->num_pins; i++) {
- err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
- &group->pins[i]);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property");
- return -EINVAL;
- }
- }
-
- group->num_pins = len;
-
- err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property");
- return -EINVAL;
- }
-
- group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
-
- return 0;
-}
-
-static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
- const char *name)
-{
- unsigned int i;
-
- for (i = 0; i < padctl->num_functions; i++)
- if (strcmp(name, padctl->functions[i]) == 0)
- return i;
-
- return -ENOENT;
-}
-
-static int
-tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
- const struct tegra_xusb_padctl_lane *lane,
- const char *name)
-{
- unsigned int i;
- int func;
-
- func = tegra_xusb_padctl_find_function(padctl, name);
- if (func < 0)
- return func;
-
- for (i = 0; i < lane->num_funcs; i++)
- if (lane->funcs[i] == func)
- return i;
-
- return -ENOENT;
-}
-
-static int
-tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
- const struct tegra_xusb_padctl_group *group)
-{
- unsigned int i;
-
- for (i = 0; i < group->num_pins; i++) {
- const struct tegra_xusb_padctl_lane *lane;
- unsigned int func;
- u32 value;
-
- lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
- if (!lane) {
- error("tegra-xusb-padctl: no lane for pin %s",
- group->pins[i]);
- continue;
- }
-
- func = tegra_xusb_padctl_lane_find_function(padctl, lane,
- group->func);
- if (func < 0) {
- error("tegra-xusb-padctl: function %s invalid for lane %s: %d",
- group->func, lane->name, func);
- continue;
- }
-
- value = padctl_readl(padctl, lane->offset);
-
- /* set pin function */
- value &= ~(lane->mask << lane->shift);
- value |= func << lane->shift;
-
- /*
- * Set IDDQ if supported on the lane and specified in the
- * configuration.
- */
- if (lane->iddq > 0 && group->iddq >= 0) {
- if (group->iddq != 0)
- value &= ~(1 << lane->iddq);
- else
- value |= 1 << lane->iddq;
- }
-
- padctl_writel(padctl, value, lane->offset);
- }
-
- return 0;
-}
-
-static int
-tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
- struct tegra_xusb_padctl_config *config)
-{
- unsigned int i;
-
- for (i = 0; i < config->num_groups; i++) {
- const struct tegra_xusb_padctl_group *group;
- int err;
-
- group = &config->groups[i];
-
- err = tegra_xusb_padctl_group_apply(padctl, group);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to apply group %s: %d",
- group->name, err);
- continue;
- }
- }
-
- return 0;
-}
-
-static int
-tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
- struct tegra_xusb_padctl_config *config,
- const void *fdt, int node)
-{
- int subnode;
-
- config->name = fdt_get_name(fdt, node, NULL);
-
- fdt_for_each_subnode(fdt, subnode, node) {
- struct tegra_xusb_padctl_group *group;
- int err;
-
- group = &config->groups[config->num_groups];
-
- err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
- subnode);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse group %s",
- group->name);
- return err;
- }
-
- config->num_groups++;
- }
-
- return 0;
-}
-
-static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
- const void *fdt, int node)
-{
- int subnode, err;
-
- err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
- if (err < 0) {
- error("tegra-xusb-padctl: registers not found");
- return err;
- }
-
- fdt_for_each_subnode(fdt, subnode, node) {
- struct tegra_xusb_padctl_config *config = &padctl->config;
-
- err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
- subnode);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse entry %s: %d",
- config->name, err);
- continue;
- }
- }
-
- return 0;
-}
-
-static int process_nodes(const void *fdt, int nodes[], unsigned int count)
-{
- unsigned int i;
-
- for (i = 0; i < count; i++) {
- enum fdt_compat_id id;
- int err;
-
- if (!fdtdec_get_is_enabled(fdt, nodes[i]))
- continue;
-
- id = fdtdec_lookup(fdt, nodes[i]);
- switch (id) {
- case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
- break;
-
- default:
- error("tegra-xusb-padctl: unsupported compatible: %s",
- fdtdec_get_compatible(id));
- continue;
- }
-
- padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
- padctl->lanes = tegra124_lanes;
-
- padctl->num_functions = ARRAY_SIZE(tegra124_functions);
- padctl->functions = tegra124_functions;
-
- err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse DT: %d",
- err);
- continue;
- }
-
- /* deassert XUSB padctl reset */
- reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
-
- err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to apply pinmux: %d",
- err);
- continue;
- }
-
- /* only a single instance is supported */
- break;
- }
-
- return 0;
-}
-
-struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
-{
- struct tegra_xusb_phy *phy = NULL;
-
- switch (type) {
- case TEGRA_XUSB_PADCTL_PCIE:
- phy = &padctl->phys[0];
- phy->padctl = padctl;
- break;
-
- case TEGRA_XUSB_PADCTL_SATA:
- phy = &padctl->phys[1];
- phy->padctl = padctl;
- break;
- }
-
- return phy;
-}
-
-int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->prepare)
- return phy->ops->prepare(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->enable)
- return phy->ops->enable(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->disable)
- return phy->ops->disable(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->unprepare)
- return phy->ops->unprepare(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-void tegra_xusb_padctl_init(const void *fdt)
-{
- int count, nodes[1];
-
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (process_nodes(fdt, nodes, count))
- return;
-}
generated by cgit (git 2.34.1) at 2024-12-26 13:16:45 +0000