diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/nonsec_virt.S | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/Kconfig | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index bee9318f5a..085649e712 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -46,7 +46,7 @@ void reset_cpu(ulong addr) int arch_cpu_init(void) { /* - * It might be necessary to flush data cache, if U-boot is loaded + * It might be necessary to flush data cache, if U-Boot is loaded * from kickstart bootloader, e.g. from S1L loader */ flush_dcache_all(); diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S index 4b8053e3f9..b21abc3752 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -41,5 +41,5 @@ lowlevel_init: orr r0, #0x00000004 str r0, [r1] - /* Return to U-boot via saved link register */ + /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 31d1c9e348..b7563edbe6 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -37,7 +37,7 @@ _monitor_vectors: /* * secure monitor handler - * U-boot calls this "software interrupt" in start.S + * U-Boot calls this "software interrupt" in start.S * This is executed on a "smc" instruction, we use a "smc #0" to switch * to non-secure state. * r0, r1, r2: passed to the callee diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4cd84b0311..3d19bbfbe2 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -1,6 +1,6 @@ if ARM64 config ARMV8_MULTIENTRY - boolean "Enable multiple CPUs to enter into U-boot" + boolean "Enable multiple CPUs to enter into U-Boot" endif |