diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx5/clock.c | 72 | ||||
| -rw-r--r-- | arch/arm/cpu/pxa/usb.c | 6 |
2 files changed, 75 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 933ce05b76..e92f10623a 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -50,6 +50,78 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; +void set_usboh3_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1) & + ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + writel(reg, &mxc_ccm->cscmr1); + + reg = readl(&mxc_ccm->cscdr1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + + writel(reg, &mxc_ccm->cscdr1); +} + +void enable_usboh3_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR2); + if (enable) + reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET); + writel(reg, &mxc_ccm->CCGR2); +} + +void set_usb_phy1_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, &mxc_ccm->cscmr1); +} + +void enable_usb_phy1_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET); + writel(reg, &mxc_ccm->CCGR4); +} + +void set_usb_phy2_clk(void) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->cscmr1); + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + writel(reg, &mxc_ccm->cscmr1); +} + +void enable_usb_phy2_clk(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&mxc_ccm->CCGR4); + if (enable) + reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET; + else + reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET); + writel(reg, &mxc_ccm->CCGR4); +} + /* * Calculate the frequency of PLLn. */ diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index 83022e2e56..307fc6ceec 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -55,7 +55,7 @@ int usb_cpu_init(void) while (readl(UHCHR) & UHCHR_FSBIR) udelay(1); -#if defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_CPU_PXA27X) @@ -72,10 +72,10 @@ int usb_cpu_stop(void) udelay(11); writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS); + writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS); udelay(10); -#if defined(CONFIG_CPU_MONAHANS) +#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_CPU_PXA27X) |