diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 122 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c | 73 |
2 files changed, 71 insertions, 124 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index 327ff97a87..c7ec70f8ca 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -29,6 +29,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/ddr2_defs.h> #include <asm/arch/emif_defs.h> +#include <asm/arch/pll_defs.h> void da850_waitloop(unsigned long loopcnt) { @@ -42,18 +43,18 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) { if (reg == davinci_pllc0_regs) /* Unlock PLL registers. */ - clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010); + clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); /* * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled * through MMR */ - clrbits_le32(®->pllctl, 0x00000020); + clrbits_le32(®->pllctl, PLLCTL_PLLENSRC); /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */ - clrbits_le32(®->pllctl, 0x00000200); + clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC); /* Set PLLEN=0 => PLL BYPASS MODE */ - clrbits_le32(®->pllctl, 0x00000001); + clrbits_le32(®->pllctl, PLLCTL_PLLEN); da850_waitloop(150); @@ -62,42 +63,43 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) * Select the Clock Mode bit 8 as External Clock or On Chip * Oscilator */ - dv_maskbits(®->pllctl, 0xFFFFFEFF); - setbits_le32(®->pllctl, (CONFIG_SYS_DV_CLKMODE << 8)); + dv_maskbits(®->pllctl, ~PLLCTL_RES_9); + setbits_le32(®->pllctl, + (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT)); } /* Clear PLLRST bit to reset the PLL */ - clrbits_le32(®->pllctl, 0x00000008); + clrbits_le32(®->pllctl, PLLCTL_PLLRST); /* Disable the PLL output */ - setbits_le32(®->pllctl, 0x00000010); + setbits_le32(®->pllctl, PLLCTL_PLLDIS); /* PLL initialization sequence */ /* * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of * power down bit */ - clrbits_le32(®->pllctl, 0x00000002); + clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN); /* Enable the PLL from Disable Mode PLLDIS bit to 0 */ - clrbits_le32(®->pllctl, 0x00000010); + clrbits_le32(®->pllctl, PLLCTL_PLLDIS); /* Program the required multiplier value in PLLM */ writel(pllmult, ®->pllm); /* program the postdiv */ if (reg == davinci_pllc0_regs) - writel((0x8000 | CONFIG_SYS_DA850_PLL0_POSTDIV), + writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV), ®->postdiv); else - writel((0x8000 | CONFIG_SYS_DA850_PLL1_POSTDIV), + writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV), ®->postdiv); /* * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that * no GO operation is currently in progress */ - while ((readl(®->pllstat) & 0x1) == 1) + while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) ; if (reg == davinci_pllc0_regs) { @@ -118,20 +120,20 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) * Set the GOSET bit in PLLCMD to 1 to initiate a new divider * transition. */ - setbits_le32(®->pllcmd, 0x01); + setbits_le32(®->pllcmd, PLLCMD_GOSTAT); /* * Wait for the GOSTAT bit in PLLSTAT to clear to 0 * (completion of phase alignment). */ - while ((readl(®->pllstat) & 0x1) == 1) + while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT) ; /* Wait for PLL to reset properly. See PLL spec for PLL reset time */ da850_waitloop(200); /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */ - setbits_le32(®->pllctl, 0x00000008); + setbits_le32(®->pllctl, PLLCTL_PLLRST); /* Wait for PLL to lock. See PLL spec for PLL lock time */ da850_waitloop(2400); @@ -140,7 +142,7 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass * mode */ - setbits_le32(®->pllctl, 0x00000001); + setbits_le32(®->pllctl, PLLCTL_PLLEN); /* @@ -148,12 +150,13 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) * run off SYSCLK */ if (reg == davinci_pllc0_regs) - dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8); + dv_maskbits(&davinci_syscfg_regs->cfgchip3, + ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC)); return 0; } -int da850_ddr_setup(unsigned int freq) +int da850_ddr_setup(void) { unsigned long tmp; @@ -197,8 +200,8 @@ int da850_ddr_setup(unsigned int freq) * the timing registers */ tmp = CONFIG_SYS_DA850_DDR2_SDBCR; - tmp &= ~(0x1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT); - tmp |= (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT); + tmp &= ~DV_DDR_BOOTUNLOCK; + tmp |= DV_DDR_TIMUNLOCK; writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ @@ -207,7 +210,7 @@ int da850_ddr_setup(unsigned int freq) writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); /* clear the TIMUNLOCK bit and write the value of the CL field */ - tmp &= ~(0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT); + tmp &= ~DV_DDR_TIMUNLOCK; writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* @@ -225,8 +228,9 @@ int da850_ddr_setup(unsigned int freq) lpsc_on(DAVINCI_LPSC_DDR_EMIF); /* disable self refresh */ - clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000); - writel(0x30, &dv_ddr2_regs_ctrl->pbbpr); + clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, + DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN); + writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; } @@ -244,57 +248,14 @@ void board_gpio_init(void) return; } -#if defined(CONFIG_NAND_SPL) -void nand_boot(void) -{ - __attribute__((noreturn)) void (*uboot)(void); - - /* copy image from NOR to RAM */ - memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, - (void *)CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE); - - /* and jump to it ... */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; - (*uboot)(); -} -#endif - -#if defined(CONFIG_NAND_SPL) -void board_init_f(ulong bootflag) -#else int arch_cpu_init(void) -#endif { - /* - * copied from arch/arm/cpu/arm926ejs/start.S - * - * flush v4 I/D caches - */ - asm("mov r0, #0"); - asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */ - asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - asm("mrc p15, 0, r0, c1, c0, 0"); - /* clear bits 13, 9:8 (--V- --RS) */ - asm("bic r0, r0, #0x00002300"); - /* clear bits 7, 2:0 (B--- -CAM) */ - asm("bic r0, r0, #0x00000087"); - /* set bit 2 (A) Align */ - asm("orr r0, r0, #0x00000002"); - /* set bit 12 (I) I-Cache */ - asm("orr r0, r0, #0x00001000"); - asm("mcr p15, 0, r0, c1, c0, 0"); - /* Unlock kick registers */ - writel(0x83e70b13, &davinci_syscfg_regs->kick0); - writel(0x95a4f1e0, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); dv_maskbits(&davinci_syscfg_regs->suspsrc, - ((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16))); + CONFIG_SYS_DA850_SYSCFG_SUSPSRC); /* Setup Pinmux */ da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0); @@ -326,10 +287,14 @@ int arch_cpu_init(void) board_gpio_init(); /* setup CSn config */ +#if defined(CONFIG_SYS_DA850_CS2CFG) writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); +#endif +#if defined(CONFIG_SYS_DA850_CS3CFG) writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); +#endif - lpsc_on(DAVINCI_LPSC_UART2); + lpsc_on(CONFIG_SYS_DA850_LPSC_UART); NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); @@ -337,17 +302,10 @@ int arch_cpu_init(void) * Fix Power and Emulation Management Register * see sprufw3a.pdf page 37 Table 24 */ - writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001, - (CONFIG_SYS_NS16550_COM1 + 0x30)); -#if defined(CONFIG_NAND_SPL) - puts("ddr init\n"); - da850_ddr_setup(132); + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart2_ctrl_regs->pwremu_mgmt); - puts("boot u-boot ...\n"); - - nand_boot(); -#else - da850_ddr_setup(132); + da850_ddr_setup(); return 0; -#endif } diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c index 3772e64cc4..6e998ded99 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -45,7 +45,8 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll0_regs->pllctl, clksrc << 8); + setbits_le32(&dv_pll0_regs->pllctl, + clksrc << PLLCTL_CLOCK_MODE_SHIFT); /* * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled @@ -82,7 +83,7 @@ int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); /* Program the PostDiv for PLL1 */ - writel(0x8000, &dv_pll0_regs->postdiv); + writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); /* Post divider setting for PLL1 */ writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1); @@ -126,7 +127,8 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv) * VDB has input on MXI pin */ clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll1_regs->pllctl, clksrc << 8); + setbits_le32(&dv_pll1_regs->pllctl, + clksrc << PLLCTL_CLOCK_MODE_SHIFT); /* * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled @@ -151,7 +153,7 @@ int dm365_pll2_init(unsigned long pllm, unsigned long prediv) writel(pllm, &dv_pll1_regs->pllm); writel(prediv, &dv_pll1_regs->prediv); - writel(0x8000, &dv_pll1_regs->postdiv); + writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | @@ -261,21 +263,23 @@ void dm365_vpss_sync_reset(void) VPSS_CLK_CTL_VPSS_CLKMD); /* LPSC SyncReset DDR Clock Enable */ - writel(((readl(&dv_psc_regs->mdctl[47]) & ~PSC_MD_STATE_MSK) | - PSC_SYNCRESET), &dv_psc_regs->mdctl[47]); + writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) & + ~PSC_MD_STATE_MSK) | PSC_SYNCRESET), + &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]); writel((1 << PdNum), &dv_psc_regs->ptcmd); while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0)) ; - while (!((readl(&dv_psc_regs->mdstat[47]) & PSC_MD_STATE_MSK) == - PSC_SYNCRESET)) + while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) & + PSC_MD_STATE_MSK) == PSC_SYNCRESET)) ; } void dm365_por_reset(void) { - if (readl(&dv_pll0_regs->rstype) & 3) + if (readl(&dv_pll0_regs->rstype) & + (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) dm365_vpss_sync_reset(); } @@ -291,19 +295,20 @@ void dm365_psc_init(void) for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) { if (lpscgroup == 0) { - lpsc_start = 0; /* Enabling LPSC 3 to 28 SCR first */ - lpsc_end = 28; + /* Enabling LPSC 3 to 28 SCR first */ + lpsc_start = DAVINCI_LPSC_VPSSMSTR; + lpsc_end = DAVINCI_LPSC_TIMER1; } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */ - lpsc_start = 38; - lpsc_end = 47; + lpsc_start = DAVINCI_LPSC_CFG5; + lpsc_end = DAVINCI_LPSC_VPSSMASTER; } else { - lpsc_start = 50; - lpsc_end = 51; + lpsc_start = DAVINCI_LPSC_MJCP; + lpsc_end = DAVINCI_LPSC_HDVICP; } /* NEXT=0x3, Enable LPSC's */ for (i = lpsc_start; i <= lpsc_end; i++) - setbits_le32(&dv_psc_regs->mdctl[i], 0x3); + setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE); /* * Program goctl to start transition sequence for LPSCs @@ -322,7 +327,7 @@ void dm365_psc_init(void) /* Wait for MODSTAT = ENABLE from LPSC's */ for (i = lpsc_start; i <= lpsc_end; i++) while (!((readl(&dv_psc_regs->mdstat[i]) & - PSC_MD_STATE_MSK) == 0x3)) + PSC_MD_STATE_MSK) == PSC_ENABLE)) ; } } @@ -332,7 +337,7 @@ static void dm365_emif_init(void) writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr); writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr); - setbits_le32(&davinci_emif_regs->nandfcr, 1); + setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND); writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr); @@ -361,31 +366,12 @@ int post_log(char *format, ...) void dm36x_lowlevel_init(ulong bootflag) { - /* - * copied from arch/arm/cpu/arm926ejs/start.S - * - * flush v4 I/D caches - */ - asm("mov r0, #0"); - asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */ - asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - asm("mrc p15, 0, r0, c1, c0, 0"); - /* clear bits 13, 9:8 (--V- --RS) */ - asm("bic r0, r0, #0x00002300"); - /* clear bits 7, 2:0 (B--- -CAM) */ - asm("bic r0, r0, #0x00000087"); - /* set bit 2 (A) Align */ - asm("orr r0, r0, #0x00000002"); - /* set bit 12 (I) I-Cache */ - asm("orr r0, r0, #0x00001000"); - asm("mcr p15, 0, r0, c1, c0, 0"); + struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs = + (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 + + DAVINCI_UART_CTRL_BASE); /* Mask all interrupts */ - writel(0x04, &dv_aintc_regs->intctl); + writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl); writel(0x0, &dv_aintc_regs->eabase); writel(0x0, &dv_aintc_regs->eint0); writel(0x0, &dv_aintc_regs->eint1); @@ -422,7 +408,10 @@ void dm36x_lowlevel_init(ulong bootflag) * Fix Power and Emulation Management Register * see sprufh2.pdf page 38 Table 22 */ - writel(0x0000e003, (CONFIG_SYS_NS16550_COM1 + 0x30)); + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), + &davinci_uart_ctrl_regs->pwremu_mgmt); + puts("ddr init\n"); dm365_ddr_setup(); |