diff options
Diffstat (limited to 'arch/arm/dts/uniphier-pxs3.dtsi')
| -rw-r--r-- | arch/arm/dts/uniphier-pxs3.dtsi | 52 |
1 files changed, 43 insertions, 9 deletions
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index 87ab5e7ff8..d4c458a211 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs3 SoC - * - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs3 SoC +// +// Copyright (C) 2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> @@ -361,7 +359,7 @@ cap-sd-highspeed; }; - soc-glue@5f800000 { + soc_glue: soc-glue@5f800000 { compatible = "socionext,uniphier-pxs3-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -425,6 +423,42 @@ }; }; + eth0: ethernet@65000000 { + compatible = "socionext,uniphier-pxs3-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + eth1: ethernet@65200000 { + compatible = "socionext,uniphier-pxs3-ave4"; + status = "disabled"; + reg = <0x65200000 0x8500>; + interrupts = <0 67 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether1_rgmii>; + clocks = <&sys_clk 7>; + resets = <&sys_rst 7>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; |