diff options
Diffstat (limited to 'arch/arm/dts/zynq-syzygy-hub.dts')
| -rw-r--r-- | arch/arm/dts/zynq-syzygy-hub.dts | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/dts/zynq-syzygy-hub.dts b/arch/arm/dts/zynq-syzygy-hub.dts new file mode 100644 index 0000000000..ebd08b4f40 --- /dev/null +++ b/arch/arm/dts/zynq-syzygy-hub.dts @@ -0,0 +1,72 @@ +/* + * SYZYGY Hub DTS + * + * Copyright (C) 2011 - 2015 Xilinx + * Copyright (C) 2017 Opal Kelly Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "SYZYGY Hub"; + compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 47 1>; + }; +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; + usb-phy = <&usb_phy0>; +}; |