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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi91
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk.dtsi3
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts2
-rw-r--r--arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi17
-rw-r--r--arch/arm/dts/socfpga_cyclone5_mcv.dtsi22
-rw-r--r--arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi34
-rw-r--r--arch/arm/dts/socfpga_cyclone5_mcvevk.dts81
8 files changed, 233 insertions, 18 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83058c4452..0ec7bc987d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -296,6 +296,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
+ socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
new file mode 100644
index 0000000000..ef215230c2
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+
+/ {
+ chosen {
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ altera_arria10_hps_eosc1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_cb_intosc_ls {
+ u-boot,dm-pre-reloc;
+ };
+
+ altera_arria10_hps_f2h_free {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clock_manager@0xffd04000 {
+ u-boot,dm-pre-reloc;
+
+ mainpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ perpll {
+ u-boot,dm-pre-reloc;
+ };
+
+ alteragrp {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ pinmux@0xffd07000 {
+ u-boot,dm-pre-reloc;
+
+ shared {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated {
+ u-boot,dm-pre-reloc;
+ };
+
+ dedicated_cfg {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpga {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ noc@0xffd10000 {
+ u-boot,dm-pre-reloc;
+
+ firewall {
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ fpgabridge@0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@2 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@3 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@4 {
+ u-boot,dm-pre-reloc;
+ };
+
+ fpgabridge@5 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 42e888548e..6e5578d7bd 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -14,7 +14,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+
+#include "socfpga_arria10.dtsi"
/ {
model = "Altera SOCFPGA Arria 10";
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index cc761967c7..d6b6c2ddc0 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -17,6 +17,8 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
/ {
chosen {
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
index 39009654d9..0446fd441e 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
@@ -11,8 +11,6 @@
*</auto-generated>
*/
-#include "socfpga_arria10.dtsi"
-
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -24,13 +22,11 @@
/* Clock sources */
clocks {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
/* Clock source: altera_arria10_hps_eosc1 */
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
@@ -39,7 +35,6 @@
/* Clock source: altera_arria10_hps_cb_intosc_ls */
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
@@ -48,7 +43,6 @@
/* Clock source: altera_arria10_hps_f2h_free */
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
- u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
@@ -62,14 +56,12 @@
* Binding: device
*/
i_clk_mgr: clock_manager@0xffd04000 {
- u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
mainpll {
- u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <191>; /* Field: vco1.numer */
@@ -98,7 +90,6 @@
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
perpll {
- u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <159>; /* Field: vco1.numer */
@@ -124,7 +115,6 @@
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
alteragrp {
- u-boot,dm-pre-reloc;
nocclk = <0x0384000b>; /* Register: nocclk */
mpuclk = <0x03840001>; /* Register: mpuclk */
};
@@ -136,7 +126,6 @@
* Binding: pinmux
*/
i_io48_pin_mux: pinmux@0xffd07000 {
- u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "pinctrl-single";
@@ -145,7 +134,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
shared {
- u-boot,dm-pre-reloc;
reg = <0xffd07000 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
@@ -202,7 +190,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated {
- u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
@@ -225,7 +212,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated_cfg {
- u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
@@ -252,7 +238,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
fpga {
- u-boot,dm-pre-reloc;
reg = <0xffd07400 0x00000100>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000001>;
@@ -283,13 +268,11 @@
* Binding: device
*/
i_noc: noc@0xffd10000 {
- u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
firewall {
- u-boot,dm-pre-reloc;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
diff --git a/arch/arm/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
new file mode 100644
index 0000000000..bd92806ffc
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mcv.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Aries/DENX MCV";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1 GiB */
+ };
+};
+
+&mmc0 { /* On-SoM eMMC */
+ bus-width = <8>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
new file mode 100644
index 0000000000..eea453b8ad
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2019 Wolfgang Grandegger <wg@aries-embedded.de>
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
new file mode 100644
index 0000000000..ceaec29770
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+
+#include "socfpga_cyclone5_mcv.dtsi"
+
+/ {
+ model = "Aries/DENX MCV EVK";
+ compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
+
+ aliases {
+ ethernet0 = &gmac0;
+ stmpe-i2c0 = &stmpe1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&gmac0 {
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&gpio0 { /* GPIO 0 ... 28 */
+ status = "okay";
+};
+
+&gpio1 { /* GPIO 29 ... 57 */
+ status = "okay";
+};
+
+&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ stmpe1: stmpe811@41 {
+ compatible = "st,stmpe811";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ id = <0>;
+ blocks = <0x5>;
+ irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <3>;
+ ts,settling = <4>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
generated by cgit (git 2.34.1) at 2024-12-27 15:39:11 +0000