diff options
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape')
6 files changed, 155 insertions, 82 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 23faffd9fc..8a05148136 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -257,6 +257,7 @@ #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h new file mode 100644 index 0000000000..a70c866651 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _FSL_ICID_H_ +#define _FSL_ICID_H_ + +#include <asm/types.h> +#include <fsl_qbman.h> +#include <fsl_sec.h> + +struct icid_id_table { + const char *compat; + u32 id; + u32 reg; + phys_addr_t compat_addr; + phys_addr_t reg_addr; +}; + +struct fman_icid_id_table { + u32 port_id; + u32 icid; +}; + +u32 get_ppid_icid(int ppid_tbl_idx, int ppid); +int fdt_get_smmu_phandle(void *blob); +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); +void set_icids(void); +void fdt_fixup_icid(void *blob); + +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \ + { .compat = name, \ + .id = idA, \ + .reg = regA, \ + .compat_addr = compataddr, \ + .reg_addr = addr, \ + } + +#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ + SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ + offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ + compataddr) + +#define SET_USB_ICID(usb_num, compat, streamid) \ + SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ + CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + +#define SET_SATA_ICID(compat, streamid) \ + SET_SCFG_ICID(compat, streamid, sata_icid,\ + AHCI_BASE_ADDR) + +#define SET_SDHC_ICID(streamid) \ + SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ + CONFIG_SYS_FSL_ESDHC_ADDR) + +#define SET_QDMA_ICID(compat, streamid) \ + SET_SCFG_ICID(compat, streamid, dma_icid,\ + QDMA_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ + EDMA_BASE_ADDR) + +#define SET_ETR_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, etr_icid, 0) + +#define SET_DEBUG_ICID(streamid) \ + SET_SCFG_ICID(NULL, streamid, debug_icid, 0) + +#define SET_QMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ + offsetof(struct ccsr_qman, liodnr) + \ + CONFIG_SYS_FSL_QMAN_ADDR, \ + CONFIG_SYS_FSL_QMAN_ADDR) + +#define SET_BMAN_ICID(streamid) \ + SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ + offsetof(struct ccsr_bman, liodnr) + \ + CONFIG_SYS_FSL_BMAN_ADDR, \ + CONFIG_SYS_FSL_BMAN_ADDR) + +#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ + { .port_id = (_port_id), .icid = (streamid) } + +#define SET_SEC_QI_ICID(streamid) \ + SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ + (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, qilcr_ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, \ + CONFIG_SYS_FSL_SEC_ADDR) + +#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ + SET_ICID_ENTRY("fsl,sec-v4.0-job-ring", streamid, \ + (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, \ + FSL_SEC_JR##jr_num##_BASE_ADDR) + +#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, 0) + +#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ + SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \ + offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ + CONFIG_SYS_FSL_SEC_ADDR, 0) + +extern struct icid_id_table icid_tbl[]; +extern struct fman_icid_id_table fman_icid_tbl[]; +extern int icid_tbl_sz; +extern int fman_icid_tbl_sz; + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h new file mode 100644 index 0000000000..1577e935a6 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _FSL_PORTALS_H_ +#define _FSL_PORTALS_H_ + +struct qportal_info { + u16 dicid; /* DQRR ICID */ + u16 ficid; /* frame data ICID */ + u16 icid; + u8 sdest; +}; + +#define SET_QP_INFO(streamid, dest) \ + { .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \ + .sdest = (dest) } + +extern struct qportal_info qp_info[]; +void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size); + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 5b4767e0fe..be0a6ae363 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -57,8 +57,7 @@ #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_QMAN_MEM_BASE) +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 @@ -88,8 +87,12 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) +#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) + #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) + #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL @@ -197,10 +200,18 @@ struct sys_info { #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x720000ull +#define FSL_SEC_JR2_OFFSET 0x730000ull +#define FSL_SEC_JR3_OFFSET 0x740000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) /* Device Configuration and Pin Control */ #define DCFG_DCSR_PORCR1 0x0 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index 8ecff4d13f..a265106686 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -39,6 +39,7 @@ enum csu_cslx_ind { CSU_CSLX_ESDHC, CSU_CSLX_IFC = 45, CSU_CSLX_I2C1, + CSU_CSLX_USB_2, CSU_CSLX_I2C3 = 48, CSU_CSLX_I2C2, CSU_CSLX_DUART2 = 50, @@ -87,84 +88,4 @@ enum csu_cslx_ind { CSU_CSLX_DSCR = 121, }; -static struct csu_ns_dev ns_dev[] = { - {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, - {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, - {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, - {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, - {CSU_CSLX_OCRAM, CSU_ALL_RW}, - {CSU_CSLX_GIC, CSU_ALL_RW}, - {CSU_CSLX_PCIE1, CSU_ALL_RW}, - {CSU_CSLX_OCRAM2, CSU_ALL_RW}, - {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, - {CSU_CSLX_PCIE2, CSU_ALL_RW}, - {CSU_CSLX_SATA, CSU_ALL_RW}, - {CSU_CSLX_USB1, CSU_ALL_RW}, - {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, - {CSU_CSLX_PCIE3, CSU_ALL_RW}, - {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, - {CSU_CSLX_USB3, CSU_ALL_RW}, - {CSU_CSLX_USB2, CSU_ALL_RW}, - {CSU_CSLX_PFE, CSU_ALL_RW}, - {CSU_CSLX_SERDES, CSU_ALL_RW}, - {CSU_CSLX_QDMA, CSU_ALL_RW}, - {CSU_CSLX_LPUART2, CSU_ALL_RW}, - {CSU_CSLX_LPUART1, CSU_ALL_RW}, - {CSU_CSLX_LPUART4, CSU_ALL_RW}, - {CSU_CSLX_LPUART3, CSU_ALL_RW}, - {CSU_CSLX_LPUART6, CSU_ALL_RW}, - {CSU_CSLX_LPUART5, CSU_ALL_RW}, - {CSU_CSLX_DSPI1, CSU_ALL_RW}, - {CSU_CSLX_QSPI, CSU_ALL_RW}, - {CSU_CSLX_ESDHC, CSU_ALL_RW}, - {CSU_CSLX_IFC, CSU_ALL_RW}, - {CSU_CSLX_I2C1, CSU_ALL_RW}, - {CSU_CSLX_I2C3, CSU_ALL_RW}, - {CSU_CSLX_I2C2, CSU_ALL_RW}, - {CSU_CSLX_DUART2, CSU_ALL_RW}, - {CSU_CSLX_DUART1, CSU_ALL_RW}, - {CSU_CSLX_WDT2, CSU_ALL_RW}, - {CSU_CSLX_WDT1, CSU_ALL_RW}, - {CSU_CSLX_EDMA, CSU_ALL_RW}, - {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, - {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, - {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, - {CSU_CSLX_DDR, CSU_ALL_RW}, - {CSU_CSLX_QUICC, CSU_ALL_RW}, - {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, - {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, - {CSU_CSLX_SFP, CSU_ALL_RW}, - {CSU_CSLX_TMU, CSU_ALL_RW}, - {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, - {CSU_CSLX_SCFG, CSU_ALL_RW}, - {CSU_CSLX_FM, CSU_ALL_RW}, - {CSU_CSLX_SEC5_5, CSU_ALL_RW}, - {CSU_CSLX_BM, CSU_ALL_RW}, - {CSU_CSLX_QM, CSU_ALL_RW}, - {CSU_CSLX_GPIO2, CSU_ALL_RW}, - {CSU_CSLX_GPIO1, CSU_ALL_RW}, - {CSU_CSLX_GPIO4, CSU_ALL_RW}, - {CSU_CSLX_GPIO3, CSU_ALL_RW}, - {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, - {CSU_CSLX_CSU, CSU_ALL_RW}, - {CSU_CSLX_IIC4, CSU_ALL_RW}, - {CSU_CSLX_WDT4, CSU_ALL_RW}, - {CSU_CSLX_WDT3, CSU_ALL_RW}, - {CSU_CSLX_ESDHC2, CSU_ALL_RW}, - {CSU_CSLX_WDT5, CSU_ALL_RW}, - {CSU_CSLX_SAI2, CSU_ALL_RW}, - {CSU_CSLX_SAI1, CSU_ALL_RW}, - {CSU_CSLX_SAI4, CSU_ALL_RW}, - {CSU_CSLX_SAI3, CSU_ALL_RW}, - {CSU_CSLX_FTM2, CSU_ALL_RW}, - {CSU_CSLX_FTM1, CSU_ALL_RW}, - {CSU_CSLX_FTM4, CSU_ALL_RW}, - {CSU_CSLX_FTM3, CSU_ALL_RW}, - {CSU_CSLX_FTM6, CSU_ALL_RW}, - {CSU_CSLX_FTM5, CSU_ALL_RW}, - {CSU_CSLX_FTM8, CSU_ALL_RW}, - {CSU_CSLX_FTM7, CSU_ALL_RW}, - {CSU_CSLX_DSCR, CSU_ALL_RW}, -}; - #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index 61c6e533c6..1b02d484d9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -50,6 +50,7 @@ #define FSL_QDMA_STREAM_ID 7 #define FSL_EDMA_STREAM_ID 8 #define FSL_ETR_STREAM_ID 9 +#define FSL_DEBUG_STREAM_ID 10 /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 11 |