diff options
Diffstat (limited to 'arch/arm/include/asm/arch-keystone')
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware-k2e.h | 44 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 44 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware.h | 61 |
3 files changed, 105 insertions, 44 deletions
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h new file mode 100644 index 0000000000..62172a4b84 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -0,0 +1,44 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index e7dff059b8..eb132f73e6 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -10,46 +10,16 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define KS2_PLL_CNTRL_BASE 0x02310000 -#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE -#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 - -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) - #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) #define KS2_ARM_PLL_EN BIT(13) -#define KS2_SPI0_BASE 0x21000400 -#define KS2_SPI1_BASE 0x21000600 -#define KS2_SPI2_BASE 0x21000800 -#define KS2_SPI_BASE KS2_SPI0_BASE - -/* Chip configuration unlock codes and registers */ -#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KS2_KICK0_MAGIC 0x83e70b13 -#define KS2_KICK1_MAGIC 0x95a4f1e0 - /* PA SS Registers */ #define KS2_PASS_BASE 0x02000000 /* PLL control registers */ -#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) -#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_MOD 0 @@ -106,25 +76,11 @@ #define KS2_LPSC_XGE 50 #define KS2_LPSC_ARM_SREFLEX 51 -/* DDR3A definitions */ -#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 -#define KS2_DDR3A_DDRPHYC 0x02329000 /* DDR3B definitions */ #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 #define KS2_DDR3B_DDRPHYC 0x02328000 -/* Queue manager */ -#define KS2_QM_MANAGER_BASE 0x02a02000 -#define KS2_QM_DESC_SETUP_BASE 0x02a03000 -#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 -#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 - -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc00000 - /* Number of DSP cores */ #define KS2_NUM_DSPS 8 diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 133edadc2a..9c86b695b4 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -69,6 +69,11 @@ typedef volatile unsigned int *dv_reg_p; #define NOSRA_MASK 0x08000000 #define ECC_MASK 0x00000001 +/* DDR3 definitions */ +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 + #define KS2_DDR3_MIDR_OFFSET 0x00 #define KS2_DDR3_STATUS_OFFSET 0x04 #define KS2_DDR3_SDCFG_OFFSET 0x08 @@ -85,12 +90,46 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* Boot Config */ +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) + /* PSC */ #define KS2_PSC_BASE 0x02350000 #define KS2_LPSC_GEM_0 15 #define KS2_LPSC_TETRIS 52 #define KS2_TETRIS_PWR_DOMAIN 31 +/* Chip configuration unlock codes and registers */ +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 + +/* PLL control registers */ +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 + +/* SPI */ +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE + /* AEMIF */ #define KS2_AEMIF_CNTRL_BASE 0x21000a00 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE @@ -98,10 +137,24 @@ typedef volatile unsigned int *dv_reg_p; /* Flag from ks2_debug options to check if DSPs need to stay ON */ #define DBG_LEAVE_DSPS_ON 0x1 +/* Queue manager */ +#define KS2_QM_MANAGER_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 + +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 + #ifdef CONFIG_SOC_K2HK #include <asm/arch/hardware-k2hk.h> #endif +#ifdef CONFIG_SOC_K2E +#include <asm/arch/hardware-k2e.h> +#endif + #ifndef __ASSEMBLY__ static inline int cpu_is_k2hk(void) { @@ -111,6 +164,14 @@ static inline int cpu_is_k2hk(void) return (part_no == 0xb981) ? 1 : 0; } +static inline int cpu_is_k2e(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a6) ? 1 : 0; +} + static inline int cpu_revision(void) { unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); |