5 files changed, 49 insertions, 691 deletions

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index be20fc0ce6..ed7a1c8be7 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -25,6 +25,7 @@
 #ifndef _CLOCKS_OMAP4_H_
 #define _CLOCKS_OMAP4_H_
 #include <common.h>
+#include <asm/omap_common.h>
 
 /*
  * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
@@ -38,479 +39,6 @@
 #define CM_CLKMODE_DPLL_MPU		0x4A004160
 #define CM_CLKSEL_CORE			0x4A004100
 
-struct omap4_prcm_regs {
-	/* cm1.ckgen */
-	u32 cm_clksel_core;
-	u32 pad001[1];
-	u32 cm_clksel_abe;
-	u32 pad002[1];
-	u32 cm_dll_ctrl;
-	u32 pad003[3];
-	u32 cm_clkmode_dpll_core;
-	u32 cm_idlest_dpll_core;
-	u32 cm_autoidle_dpll_core;
-	u32 cm_clksel_dpll_core;
-	u32 cm_div_m2_dpll_core;
-	u32 cm_div_m3_dpll_core;
-	u32 cm_div_m4_dpll_core;
-	u32 cm_div_m5_dpll_core;
-	u32 cm_div_m6_dpll_core;
-	u32 cm_div_m7_dpll_core;
-	u32 cm_ssc_deltamstep_dpll_core;
-	u32 cm_ssc_modfreqdiv_dpll_core;
-	u32 cm_emu_override_dpll_core;
-	u32 pad004[3];
-	u32 cm_clkmode_dpll_mpu;
-	u32 cm_idlest_dpll_mpu;
-	u32 cm_autoidle_dpll_mpu;
-	u32 cm_clksel_dpll_mpu;
-	u32 cm_div_m2_dpll_mpu;
-	u32 pad005[5];
-	u32 cm_ssc_deltamstep_dpll_mpu;
-	u32 cm_ssc_modfreqdiv_dpll_mpu;
-	u32 pad006[3];
-	u32 cm_bypclk_dpll_mpu;
-	u32 cm_clkmode_dpll_iva;
-	u32 cm_idlest_dpll_iva;
-	u32 cm_autoidle_dpll_iva;
-	u32 cm_clksel_dpll_iva;
-	u32 pad007[2];
-	u32 cm_div_m4_dpll_iva;
-	u32 cm_div_m5_dpll_iva;
-	u32 pad008[2];
-	u32 cm_ssc_deltamstep_dpll_iva;
-	u32 cm_ssc_modfreqdiv_dpll_iva;
-	u32 pad009[3];
-	u32 cm_bypclk_dpll_iva;
-	u32 cm_clkmode_dpll_abe;
-	u32 cm_idlest_dpll_abe;
-	u32 cm_autoidle_dpll_abe;
-	u32 cm_clksel_dpll_abe;
-	u32 cm_div_m2_dpll_abe;
-	u32 cm_div_m3_dpll_abe;
-	u32 pad010[4];
-	u32 cm_ssc_deltamstep_dpll_abe;
-	u32 cm_ssc_modfreqdiv_dpll_abe;
-	u32 pad011[4];
-	u32 cm_clkmode_dpll_ddrphy;
-	u32 cm_idlest_dpll_ddrphy;
-	u32 cm_autoidle_dpll_ddrphy;
-	u32 cm_clksel_dpll_ddrphy;
-	u32 cm_div_m2_dpll_ddrphy;
-	u32 pad012[1];
-	u32 cm_div_m4_dpll_ddrphy;
-	u32 cm_div_m5_dpll_ddrphy;
-	u32 cm_div_m6_dpll_ddrphy;
-	u32 pad013[1];
-	u32 cm_ssc_deltamstep_dpll_ddrphy;
-	u32 pad014[5];
-	u32 cm_shadow_freq_config1;
-	u32 pad0141[47];
-	u32 cm_mpu_mpu_clkctrl;
-
-	/* cm1.dsp */
-	u32 pad015[55];
-	u32 cm_dsp_clkstctrl;
-	u32 pad016[7];
-	u32 cm_dsp_dsp_clkctrl;
-
-	/* cm1.abe */
-	u32 pad017[55];
-	u32 cm1_abe_clkstctrl;
-	u32 pad018[7];
-	u32 cm1_abe_l4abe_clkctrl;
-	u32 pad019[1];
-	u32 cm1_abe_aess_clkctrl;
-	u32 pad020[1];
-	u32 cm1_abe_pdm_clkctrl;
-	u32 pad021[1];
-	u32 cm1_abe_dmic_clkctrl;
-	u32 pad022[1];
-	u32 cm1_abe_mcasp_clkctrl;
-	u32 pad023[1];
-	u32 cm1_abe_mcbsp1_clkctrl;
-	u32 pad024[1];
-	u32 cm1_abe_mcbsp2_clkctrl;
-	u32 pad025[1];
-	u32 cm1_abe_mcbsp3_clkctrl;
-	u32 pad026[1];
-	u32 cm1_abe_slimbus_clkctrl;
-	u32 pad027[1];
-	u32 cm1_abe_timer5_clkctrl;
-	u32 pad028[1];
-	u32 cm1_abe_timer6_clkctrl;
-	u32 pad029[1];
-	u32 cm1_abe_timer7_clkctrl;
-	u32 pad030[1];
-	u32 cm1_abe_timer8_clkctrl;
-	u32 pad031[1];
-	u32 cm1_abe_wdt3_clkctrl;
-
-	/* cm2.ckgen */
-	u32 pad032[3805];
-	u32 cm_clksel_mpu_m3_iss_root;
-	u32 cm_clksel_usb_60mhz;
-	u32 cm_scale_fclk;
-	u32 pad033[1];
-	u32 cm_core_dvfs_perf1;
-	u32 cm_core_dvfs_perf2;
-	u32 cm_core_dvfs_perf3;
-	u32 cm_core_dvfs_perf4;
-	u32 pad034[1];
-	u32 cm_core_dvfs_current;
-	u32 cm_iva_dvfs_perf_tesla;
-	u32 cm_iva_dvfs_perf_ivahd;
-	u32 cm_iva_dvfs_perf_abe;
-	u32 pad035[1];
-	u32 cm_iva_dvfs_current;
-	u32 pad036[1];
-	u32 cm_clkmode_dpll_per;
-	u32 cm_idlest_dpll_per;
-	u32 cm_autoidle_dpll_per;
-	u32 cm_clksel_dpll_per;
-	u32 cm_div_m2_dpll_per;
-	u32 cm_div_m3_dpll_per;
-	u32 cm_div_m4_dpll_per;
-	u32 cm_div_m5_dpll_per;
-	u32 cm_div_m6_dpll_per;
-	u32 cm_div_m7_dpll_per;
-	u32 cm_ssc_deltamstep_dpll_per;
-	u32 cm_ssc_modfreqdiv_dpll_per;
-	u32 cm_emu_override_dpll_per;
-	u32 pad037[3];
-	u32 cm_clkmode_dpll_usb;
-	u32 cm_idlest_dpll_usb;
-	u32 cm_autoidle_dpll_usb;
-	u32 cm_clksel_dpll_usb;
-	u32 cm_div_m2_dpll_usb;
-	u32 pad038[5];
-	u32 cm_ssc_deltamstep_dpll_usb;
-	u32 cm_ssc_modfreqdiv_dpll_usb;
-	u32 pad039[1];
-	u32 cm_clkdcoldo_dpll_usb;
-	u32 pad040[2];
-	u32 cm_clkmode_dpll_unipro;
-	u32 cm_idlest_dpll_unipro;
-	u32 cm_autoidle_dpll_unipro;
-	u32 cm_clksel_dpll_unipro;
-	u32 cm_div_m2_dpll_unipro;
-	u32 pad041[5];
-	u32 cm_ssc_deltamstep_dpll_unipro;
-	u32 cm_ssc_modfreqdiv_dpll_unipro;
-
-	/* cm2.core */
-	u32 pad0411[324];
-	u32 cm_l3_1_clkstctrl;
-	u32 pad042[1];
-	u32 cm_l3_1_dynamicdep;
-	u32 pad043[5];
-	u32 cm_l3_1_l3_1_clkctrl;
-	u32 pad044[55];
-	u32 cm_l3_2_clkstctrl;
-	u32 pad045[1];
-	u32 cm_l3_2_dynamicdep;
-	u32 pad046[5];
-	u32 cm_l3_2_l3_2_clkctrl;
-	u32 pad047[1];
-	u32 cm_l3_2_gpmc_clkctrl;
-	u32 pad048[1];
-	u32 cm_l3_2_ocmc_ram_clkctrl;
-	u32 pad049[51];
-	u32 cm_mpu_m3_clkstctrl;
-	u32 cm_mpu_m3_staticdep;
-	u32 cm_mpu_m3_dynamicdep;
-	u32 pad050[5];
-	u32 cm_mpu_m3_mpu_m3_clkctrl;
-	u32 pad051[55];
-	u32 cm_sdma_clkstctrl;
-	u32 cm_sdma_staticdep;
-	u32 cm_sdma_dynamicdep;
-	u32 pad052[5];
-	u32 cm_sdma_sdma_clkctrl;
-	u32 pad053[55];
-	u32 cm_memif_clkstctrl;
-	u32 pad054[7];
-	u32 cm_memif_dmm_clkctrl;
-	u32 pad055[1];
-	u32 cm_memif_emif_fw_clkctrl;
-	u32 pad056[1];
-	u32 cm_memif_emif_1_clkctrl;
-	u32 pad057[1];
-	u32 cm_memif_emif_2_clkctrl;
-	u32 pad058[1];
-	u32 cm_memif_dll_clkctrl;
-	u32 pad059[3];
-	u32 cm_memif_emif_h1_clkctrl;
-	u32 pad060[1];
-	u32 cm_memif_emif_h2_clkctrl;
-	u32 pad061[1];
-	u32 cm_memif_dll_h_clkctrl;
-	u32 pad062[39];
-	u32 cm_c2c_clkstctrl;
-	u32 cm_c2c_staticdep;
-	u32 cm_c2c_dynamicdep;
-	u32 pad063[5];
-	u32 cm_c2c_sad2d_clkctrl;
-	u32 pad064[1];
-	u32 cm_c2c_modem_icr_clkctrl;
-	u32 pad065[1];
-	u32 cm_c2c_sad2d_fw_clkctrl;
-	u32 pad066[51];
-	u32 cm_l4cfg_clkstctrl;
-	u32 pad067[1];
-	u32 cm_l4cfg_dynamicdep;
-	u32 pad068[5];
-	u32 cm_l4cfg_l4_cfg_clkctrl;
-	u32 pad069[1];
-	u32 cm_l4cfg_hw_sem_clkctrl;
-	u32 pad070[1];
-	u32 cm_l4cfg_mailbox_clkctrl;
-	u32 pad071[1];
-	u32 cm_l4cfg_sar_rom_clkctrl;
-	u32 pad072[49];
-	u32 cm_l3instr_clkstctrl;
-	u32 pad073[7];
-	u32 cm_l3instr_l3_3_clkctrl;
-	u32 pad074[1];
-	u32 cm_l3instr_l3_instr_clkctrl;
-	u32 pad075[5];
-	u32 cm_l3instr_intrconn_wp1_clkctrl;
-
-
-	/* cm2.ivahd */
-	u32 pad076[47];
-	u32 cm_ivahd_clkstctrl;
-	u32 pad077[7];
-	u32 cm_ivahd_ivahd_clkctrl;
-	u32 pad078[1];
-	u32 cm_ivahd_sl2_clkctrl;
-
-	/* cm2.cam */
-	u32 pad079[53];
-	u32 cm_cam_clkstctrl;
-	u32 pad080[7];
-	u32 cm_cam_iss_clkctrl;
-	u32 pad081[1];
-	u32 cm_cam_fdif_clkctrl;
-
-	/* cm2.dss */
-	u32 pad082[53];
-	u32 cm_dss_clkstctrl;
-	u32 pad083[7];
-	u32 cm_dss_dss_clkctrl;
-
-	/* cm2.sgx */
-	u32 pad084[55];
-	u32 cm_sgx_clkstctrl;
-	u32 pad085[7];
-	u32 cm_sgx_sgx_clkctrl;
-
-	/* cm2.l3init */
-	u32 pad086[55];
-	u32 cm_l3init_clkstctrl;
-
-	/* cm2.l3init */
-	u32 pad087[9];
-	u32 cm_l3init_hsmmc1_clkctrl;
-	u32 pad088[1];
-	u32 cm_l3init_hsmmc2_clkctrl;
-	u32 pad089[1];
-	u32 cm_l3init_hsi_clkctrl;
-	u32 pad090[7];
-	u32 cm_l3init_hsusbhost_clkctrl;
-	u32 pad091[1];
-	u32 cm_l3init_hsusbotg_clkctrl;
-	u32 pad092[1];
-	u32 cm_l3init_hsusbtll_clkctrl;
-	u32 pad093[3];
-	u32 cm_l3init_p1500_clkctrl;
-	u32 pad094[21];
-	u32 cm_l3init_fsusb_clkctrl;
-	u32 pad095[3];
-	u32 cm_l3init_usbphy_clkctrl;
-
-	/* cm2.l4per */
-	u32 pad096[7];
-	u32 cm_l4per_clkstctrl;
-	u32 pad097[1];
-	u32 cm_l4per_dynamicdep;
-	u32 pad098[5];
-	u32 cm_l4per_adc_clkctrl;
-	u32 pad100[1];
-	u32 cm_l4per_gptimer10_clkctrl;
-	u32 pad101[1];
-	u32 cm_l4per_gptimer11_clkctrl;
-	u32 pad102[1];
-	u32 cm_l4per_gptimer2_clkctrl;
-	u32 pad103[1];
-	u32 cm_l4per_gptimer3_clkctrl;
-	u32 pad104[1];
-	u32 cm_l4per_gptimer4_clkctrl;
-	u32 pad105[1];
-	u32 cm_l4per_gptimer9_clkctrl;
-	u32 pad106[1];
-	u32 cm_l4per_elm_clkctrl;
-	u32 pad107[1];
-	u32 cm_l4per_gpio2_clkctrl;
-	u32 pad108[1];
-	u32 cm_l4per_gpio3_clkctrl;
-	u32 pad109[1];
-	u32 cm_l4per_gpio4_clkctrl;
-	u32 pad110[1];
-	u32 cm_l4per_gpio5_clkctrl;
-	u32 pad111[1];
-	u32 cm_l4per_gpio6_clkctrl;
-	u32 pad112[1];
-	u32 cm_l4per_hdq1w_clkctrl;
-	u32 pad113[1];
-	u32 cm_l4per_hecc1_clkctrl;
-	u32 pad114[1];
-	u32 cm_l4per_hecc2_clkctrl;
-	u32 pad115[1];
-	u32 cm_l4per_i2c1_clkctrl;
-	u32 pad116[1];
-	u32 cm_l4per_i2c2_clkctrl;
-	u32 pad117[1];
-	u32 cm_l4per_i2c3_clkctrl;
-	u32 pad118[1];
-	u32 cm_l4per_i2c4_clkctrl;
-	u32 pad119[1];
-	u32 cm_l4per_l4per_clkctrl;
-	u32 pad1191[3];
-	u32 cm_l4per_mcasp2_clkctrl;
-	u32 pad120[1];
-	u32 cm_l4per_mcasp3_clkctrl;
-	u32 pad121[1];
-	u32 cm_l4per_mcbsp4_clkctrl;
-	u32 pad122[1];
-	u32 cm_l4per_mgate_clkctrl;
-	u32 pad123[1];
-	u32 cm_l4per_mcspi1_clkctrl;
-	u32 pad124[1];
-	u32 cm_l4per_mcspi2_clkctrl;
-	u32 pad125[1];
-	u32 cm_l4per_mcspi3_clkctrl;
-	u32 pad126[1];
-	u32 cm_l4per_mcspi4_clkctrl;
-	u32 pad127[5];
-	u32 cm_l4per_mmcsd3_clkctrl;
-	u32 pad128[1];
-	u32 cm_l4per_mmcsd4_clkctrl;
-	u32 pad129[1];
-	u32 cm_l4per_msprohg_clkctrl;
-	u32 pad130[1];
-	u32 cm_l4per_slimbus2_clkctrl;
-	u32 pad131[1];
-	u32 cm_l4per_uart1_clkctrl;
-	u32 pad132[1];
-	u32 cm_l4per_uart2_clkctrl;
-	u32 pad133[1];
-	u32 cm_l4per_uart3_clkctrl;
-	u32 pad134[1];
-	u32 cm_l4per_uart4_clkctrl;
-	u32 pad135[1];
-	u32 cm_l4per_mmcsd5_clkctrl;
-	u32 pad136[1];
-	u32 cm_l4per_i2c5_clkctrl;
-	u32 pad137[5];
-	u32 cm_l4sec_clkstctrl;
-	u32 cm_l4sec_staticdep;
-	u32 cm_l4sec_dynamicdep;
-	u32 pad138[5];
-	u32 cm_l4sec_aes1_clkctrl;
-	u32 pad139[1];
-	u32 cm_l4sec_aes2_clkctrl;
-	u32 pad140[1];
-	u32 cm_l4sec_des3des_clkctrl;
-	u32 pad141[1];
-	u32 cm_l4sec_pkaeip29_clkctrl;
-	u32 pad142[1];
-	u32 cm_l4sec_rng_clkctrl;
-	u32 pad143[1];
-	u32 cm_l4sec_sha2md51_clkctrl;
-	u32 pad144[3];
-	u32 cm_l4sec_cryptodma_clkctrl;
-	u32 pad145[776841];
-
-	/* l4 wkup regs */
-	u32 pad201[6211];
-	u32 cm_abe_pll_ref_clksel;
-	u32 cm_sys_clksel;
-	u32 pad202[1467];
-	u32 cm_wkup_clkstctrl;
-	u32 pad203[7];
-	u32 cm_wkup_l4wkup_clkctrl;
-	u32 pad204;
-	u32 cm_wkup_wdtimer1_clkctrl;
-	u32 pad205;
-	u32 cm_wkup_wdtimer2_clkctrl;
-	u32 pad206;
-	u32 cm_wkup_gpio1_clkctrl;
-	u32 pad207;
-	u32 cm_wkup_gptimer1_clkctrl;
-	u32 pad208;
-	u32 cm_wkup_gptimer12_clkctrl;
-	u32 pad209;
-	u32 cm_wkup_synctimer_clkctrl;
-	u32 pad210;
-	u32 cm_wkup_usim_clkctrl;
-	u32 pad211;
-	u32 cm_wkup_sarram_clkctrl;
-	u32 pad212[5];
-	u32 cm_wkup_keyboard_clkctrl;
-	u32 pad213;
-	u32 cm_wkup_rtc_clkctrl;
-	u32 pad214;
-	u32 cm_wkup_bandgap_clkctrl;
-	u32 pad215[197];
-	u32 prm_vc_val_bypass;
-	u32 prm_vc_cfg_channel;
-	u32 prm_vc_cfg_i2c_mode;
-	u32 prm_vc_cfg_i2c_clk;
-
-};
-
-struct omap4_scrm_regs {
-	u32 revision;		/* 0x0000 */
-	u32 pad00[63];
-	u32 clksetuptime;	/* 0x0100 */
-	u32 pmicsetuptime;	/* 0x0104 */
-	u32 pad01[2];
-	u32 altclksrc;		/* 0x0110 */
-	u32 pad02[2];
-	u32 c2cclkm;		/* 0x011c */
-	u32 pad03[56];
-	u32 extclkreq;		/* 0x0200 */
-	u32 accclkreq;		/* 0x0204 */
-	u32 pwrreq;		/* 0x0208 */
-	u32 pad04[1];
-	u32 auxclkreq0;		/* 0x0210 */
-	u32 auxclkreq1;		/* 0x0214 */
-	u32 auxclkreq2;		/* 0x0218 */
-	u32 auxclkreq3;		/* 0x021c */
-	u32 auxclkreq4;		/* 0x0220 */
-	u32 auxclkreq5;		/* 0x0224 */
-	u32 pad05[3];
-	u32 c2cclkreq;		/* 0x0234 */
-	u32 pad06[54];
-	u32 auxclk0;		/* 0x0310 */
-	u32 auxclk1;		/* 0x0314 */
-	u32 auxclk2;		/* 0x0318 */
-	u32 auxclk3;		/* 0x031c */
-	u32 auxclk4;		/* 0x0320 */
-	u32 auxclk5;		/* 0x0324 */
-	u32 pad07[54];
-	u32 rsttime_reg;	/* 0x0400 */
-	u32 pad08[6];
-	u32 c2crstctrl;		/* 0x041c */
-	u32 extpwronrstctrl;	/* 0x0420 */
-	u32 pad09[59];
-	u32 extwarmrstst_reg;	/* 0x0510 */
-	u32 apewarmrstst_reg;	/* 0x0514 */
-	u32 pad10[1];
-	u32 c2cwarmrstst_reg;	/* 0x051C */
-};
-
 /* DPLL register offsets */
 #define CM_CLKMODE_DPLL		0
 #define CM_IDLEST_DPLL		0x4
@@ -714,54 +242,44 @@ struct omap4_scrm_regs {
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
-#define NUM_SYS_CLKS	7
-
-struct dpll_regs {
-	u32 cm_clkmode_dpll;
-	u32 cm_idlest_dpll;
-	u32 cm_autoidle_dpll;
-	u32 cm_clksel_dpll;
-	u32 cm_div_m2_dpll;
-	u32 cm_div_m3_dpll;
-	u32 cm_div_m4_dpll;
-	u32 cm_div_m5_dpll;
-	u32 cm_div_m6_dpll;
-	u32 cm_div_m7_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
-	u32 m;
-	u32 n;
-	s8 m2;
-	s8 m3;
-	s8 m4;
-	s8 m5;
-	s8 m6;
-	s8 m7;
+struct omap4_scrm_regs {
+	u32 revision;           /* 0x0000 */
+	u32 pad00[63];
+	u32 clksetuptime;       /* 0x0100 */
+	u32 pmicsetuptime;      /* 0x0104 */
+	u32 pad01[2];
+	u32 altclksrc;          /* 0x0110 */
+	u32 pad02[2];
+	u32 c2cclkm;            /* 0x011c */
+	u32 pad03[56];
+	u32 extclkreq;          /* 0x0200 */
+	u32 accclkreq;          /* 0x0204 */
+	u32 pwrreq;             /* 0x0208 */
+	u32 pad04[1];
+	u32 auxclkreq0;         /* 0x0210 */
+	u32 auxclkreq1;         /* 0x0214 */
+	u32 auxclkreq2;         /* 0x0218 */
+	u32 auxclkreq3;         /* 0x021c */
+	u32 auxclkreq4;         /* 0x0220 */
+	u32 auxclkreq5;         /* 0x0224 */
+	u32 pad05[3];
+	u32 c2cclkreq;          /* 0x0234 */
+	u32 pad06[54];
+	u32 auxclk0;            /* 0x0310 */
+	u32 auxclk1;            /* 0x0314 */
+	u32 auxclk2;            /* 0x0318 */
+	u32 auxclk3;            /* 0x031c */
+	u32 auxclk4;            /* 0x0320 */
+	u32 auxclk5;            /* 0x0324 */
+	u32 pad07[54];
+	u32 rsttime_reg;        /* 0x0400 */
+	u32 pad08[6];
+	u32 c2crstctrl;         /* 0x041c */
+	u32 extpwronrstctrl;    /* 0x0420 */
+	u32 pad09[59];
+	u32 extwarmrstst_reg;   /* 0x0510 */
+	u32 apewarmrstst_reg;   /* 0x0514 */
+	u32 pad10[1];
+	u32 c2cwarmrstst_reg;   /* 0x051C */
 };
-
-extern struct omap4_prcm_regs *const prcm;
-extern const u32 sys_clk_array[8];
-
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
-		      u32 *const *clk_modules_hw_auto,
-		      u32 *const *clk_modules_explicit_en,
-		      u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
 #endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index 2114046e71..9c8ccb6c83 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -25,6 +25,8 @@
 #ifndef MMC_HOST_DEF_H
 #define MMC_HOST_DEF_H
 
+#include <asm/omap_mmc.h>
+
 /*
  * OMAP HSMMC register definitions
  */
@@ -33,142 +35,4 @@
 #define OMAP_HSMMC2_BASE	0x480B4100
 #define OMAP_HSMMC3_BASE	0x480AD100
 
-struct hsmmc {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int sysstatus;		/* 0x14 */
-	unsigned char res2[0x14];
-	unsigned int con;		/* 0x2C */
-	unsigned char res3[0xD4];
-	unsigned int blk;		/* 0x104 */
-	unsigned int arg;		/* 0x108 */
-	unsigned int cmd;		/* 0x10C */
-	unsigned int rsp10;		/* 0x110 */
-	unsigned int rsp32;		/* 0x114 */
-	unsigned int rsp54;		/* 0x118 */
-	unsigned int rsp76;		/* 0x11C */
-	unsigned int data;		/* 0x120 */
-	unsigned int pstate;		/* 0x124 */
-	unsigned int hctl;		/* 0x128 */
-	unsigned int sysctl;		/* 0x12C */
-	unsigned int stat;		/* 0x130 */
-	unsigned int ie;		/* 0x134 */
-	unsigned char res4[0x8];
-	unsigned int capa;		/* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET			(0x1 << 1)
-#define RESETDONE			(0x1 << 0)
-#define NOOPENDRAIN			(0x0 << 0)
-#define OPENDRAIN			(0x1 << 0)
-#define OD				(0x1 << 0)
-#define INIT_NOINIT			(0x0 << 1)
-#define INIT_INITSTREAM			(0x1 << 1)
-#define HR_NOHOSTRESP			(0x0 << 2)
-#define STR_BLOCK			(0x0 << 3)
-#define MODE_FUNC			(0x0 << 4)
-#define DW8_1_4BITMODE			(0x0 << 5)
-#define MIT_CTO				(0x0 << 6)
-#define CDP_ACTIVEHIGH			(0x0 << 7)
-#define WPP_ACTIVEHIGH			(0x0 << 8)
-#define RESERVED_MASK			(0x3 << 9)
-#define CTPL_MMC_SD			(0x0 << 11)
-#define BLEN_512BYTESLEN		(0x200 << 0)
-#define NBLK_STPCNT			(0x0 << 16)
-#define DE_DISABLE			(0x0 << 0)
-#define BCE_DISABLE			(0x0 << 1)
-#define BCE_ENABLE			(0x1 << 1)
-#define ACEN_DISABLE			(0x0 << 2)
-#define DDIR_OFFSET			(4)
-#define DDIR_MASK			(0x1 << 4)
-#define DDIR_WRITE			(0x0 << 4)
-#define DDIR_READ			(0x1 << 4)
-#define MSBS_SGLEBLK			(0x0 << 5)
-#define MSBS_MULTIBLK			(0x1 << 5)
-#define RSP_TYPE_OFFSET			(16)
-#define RSP_TYPE_MASK			(0x3 << 16)
-#define RSP_TYPE_NORSP			(0x0 << 16)
-#define RSP_TYPE_LGHT136		(0x1 << 16)
-#define RSP_TYPE_LGHT48			(0x2 << 16)
-#define RSP_TYPE_LGHT48B		(0x3 << 16)
-#define CCCE_NOCHECK			(0x0 << 19)
-#define CCCE_CHECK			(0x1 << 19)
-#define CICE_NOCHECK			(0x0 << 20)
-#define CICE_CHECK			(0x1 << 20)
-#define DP_OFFSET			(21)
-#define DP_MASK				(0x1 << 21)
-#define DP_NO_DATA			(0x0 << 21)
-#define DP_DATA				(0x1 << 21)
-#define CMD_TYPE_NORMAL			(0x0 << 22)
-#define INDEX_OFFSET			(24)
-#define INDEX_MASK			(0x3f << 24)
-#define INDEX(i)			(i << 24)
-#define DATI_MASK			(0x1 << 1)
-#define CMDI_MASK			(0x1 << 0)
-#define DTW_1_BITMODE			(0x0 << 1)
-#define DTW_4_BITMODE			(0x1 << 1)
-#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF			(0x0 << 8)
-#define SDBP_PWRON			(0x1 << 8)
-#define SDVS_1V8			(0x5 << 9)
-#define SDVS_3V0			(0x6 << 9)
-#define ICE_MASK			(0x1 << 0)
-#define ICE_STOP			(0x0 << 0)
-#define ICS_MASK			(0x1 << 1)
-#define ICS_NOTREADY			(0x0 << 1)
-#define ICE_OSCILLATE			(0x1 << 0)
-#define CEN_MASK			(0x1 << 2)
-#define CEN_DISABLE			(0x0 << 2)
-#define CEN_ENABLE			(0x1 << 2)
-#define CLKD_OFFSET			(6)
-#define CLKD_MASK			(0x3FF << 6)
-#define DTO_MASK			(0xF << 16)
-#define DTO_15THDTO			(0xE << 16)
-#define SOFTRESETALL			(0x1 << 24)
-#define CC_MASK				(0x1 << 0)
-#define TC_MASK				(0x1 << 1)
-#define BWR_MASK			(0x1 << 4)
-#define BRR_MASK			(0x1 << 5)
-#define ERRI_MASK			(0x1 << 15)
-#define IE_CC				(0x01 << 0)
-#define IE_TC				(0x01 << 1)
-#define IE_BWR				(0x01 << 4)
-#define IE_BRR				(0x01 << 5)
-#define IE_CTO				(0x01 << 16)
-#define IE_CCRC				(0x01 << 17)
-#define IE_CEB				(0x01 << 18)
-#define IE_CIE				(0x01 << 19)
-#define IE_DTO				(0x01 << 20)
-#define IE_DCRC				(0x01 << 21)
-#define IE_DEB				(0x01 << 22)
-#define IE_CERR				(0x01 << 28)
-#define IE_BADA				(0x01 << 29)
-
-#define VS30_3V0SUP			(1 << 25)
-#define VS18_1V8SUP			(1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE		512
-#define MMC_CARD			0
-#define SD_CARD				1
-#define BYTE_MODE			0
-#define SECTOR_MODE			1
-#define CLK_INITSEQ			0
-#define CLK_400KHZ			1
-#define CLK_MISC			2
-
-#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE	96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
-	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index d4b5076108..5f321fe6f0 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -132,34 +132,6 @@ struct s32ktimer {
 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
 #define DEVICE_GP 0x3
 
-struct omap_sys_ctrl_regs {
-	unsigned int pad1[129];
-	unsigned int control_id_code;			/* 0x4A002204 */
-	unsigned int pad11[22];
-	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
-	unsigned int pad2[24];				/* 0x4a002264 */
-	unsigned int control_status;			/* 0x4a0022c4 */
-	unsigned int pad3[22];				/* 0x4a0022c8 */
-	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
-	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
-	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
-	unsigned int pad4[260277];
-	unsigned int control_pbiaslite;                 /* 0x4A100600 */
-	unsigned int pad5[63];
-	unsigned int control_efuse_1;			/* 0x4A100700 */
-	unsigned int control_efuse_2;			/* 0x4A100704 */
-};
-
-struct control_lpddr2io_regs {
-	unsigned int control_lpddr2io1_0;
-	unsigned int control_lpddr2io1_1;
-	unsigned int control_lpddr2io1_2;
-	unsigned int control_lpddr2io1_3;
-	unsigned int control_lpddr2io2_0;
-	unsigned int control_lpddr2io2_1;
-	unsigned int control_lpddr2io2_2;
-	unsigned int control_lpddr2io2_3;
-};
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -178,7 +150,11 @@ struct control_lpddr2io_regs {
 #define OMAP4_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
 #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
 #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP4_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
 
 /* ROM code defines */
 /* Boot device */
diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h
index cec84dc548..4e094f9c60 100644
--- a/arch/arm/include/asm/arch-omap4/spl.h
+++ b/arch/arm/include/asm/arch-omap4/spl.h
@@ -27,7 +27,7 @@
 #define BOOT_DEVICE_XIP		1
 #define BOOT_DEVICE_XIPWAIT	2
 #define BOOT_DEVICE_NAND	3
-#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_ONENAND	4
 #define BOOT_DEVICE_MMC1	5
 #define BOOT_DEVICE_MMC2	6
 #define BOOT_DEVICE_MMC2_2	0xFF
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b48f81dc33..d5f1868eee 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -44,7 +44,7 @@ void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
 u32 omap4_ddr_clk(void);