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-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h1
-rw-r--r--arch/arm/include/asm/arch-imx8/sys_proto.h9
-rw-r--r--arch/arm/include/asm/arch-imx8m/imx-regs.h41
-rw-r--r--arch/arm/include/asm/mach-imx/dma.h15
-rw-r--r--arch/arm/include/asm/mach-imx/imx-nandbcb.h4
-rw-r--r--arch/arm/include/asm/mach-imx/module_fuse.h127
-rw-r--r--arch/arm/include/asm/mach-imx/regs-apbh.h9
-rw-r--r--arch/arm/include/asm/mach-imx/regs-bch.h20
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h3
9 files changed, 202 insertions, 27 deletions
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index b52565473d..e9c0078922 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -64,6 +64,7 @@
#define CHIP_REV_A 0x0
#define CHIP_REV_B 0x1
+#define CHIP_REV_C 0x2
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 0e981ae950..6f1fc8f999 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -5,6 +5,11 @@
#include <asm/arch/sci/sci.h>
#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/power-domain.h>
+#include <dm/platdata.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+#include <power-domain.h>
#include <linux/types.h>
struct pass_over_info_t {
@@ -21,3 +26,7 @@ void build_info(void);
enum boot_device get_boot_device(void);
int print_bootinfo(void);
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
+int imx8_power_domain_lookup_name(const char *name,
+ struct power_domain *power_domain);
+void imx8_power_off_pd_devices(const char *permanent_on_devices[], int size);
+bool m4_parts_booted(void);
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 62640d996e..3cfa169c97 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -137,6 +137,40 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
};
+struct fuse_bank3_regs {
+ u32 mem_trim0;
+ u32 rsvd0[3];
+ u32 mem_trim1;
+ u32 rsvd1[3];
+ u32 mem_trim2;
+ u32 rsvd2[3];
+ u32 ana0;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank9_regs {
+ u32 mac_addr0;
+ u32 rsvd0[3];
+ u32 mac_addr1;
+ u32 rsvd1[11];
+};
+
+struct fuse_bank38_regs {
+ u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
+ u32 rsvd0[3];
+ u32 ana_trim2;
+ u32 rsvd1[3];
+ u32 ana_trim3;
+ u32 rsvd2[3];
+ u32 ana_trim4;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank39_regs {
+ u32 ana_trim5;
+ u32 rsvd[15];
+};
+
#ifdef CONFIG_IMX8MQ
struct anamix_pll {
u32 audio_pll1_cfg0;
@@ -227,13 +261,6 @@ struct anamix_pll {
};
#endif
-struct fuse_bank9_regs {
- u32 mac_addr0;
- u32 rsvd0[3];
- u32 mac_addr1;
- u32 rsvd1[11];
-};
-
/* System Reset Controller (SRC) */
struct src {
u32 scr;
diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h
index ca70731b9e..247a91afb0 100644
--- a/arch/arm/include/asm/mach-imx/dma.h
+++ b/arch/arm/include/asm/mach-imx/dma.h
@@ -7,6 +7,7 @@
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2020 NXP
*/
#ifndef __DMA_H__
@@ -53,7 +54,7 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#else
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
@@ -95,13 +96,13 @@ enum {
#define MXS_DMA_DESC_BYTES_OFFSET 16
struct mxs_dma_cmd {
- unsigned long next;
- unsigned long data;
+ u32 next;
+ u32 data;
union {
- dma_addr_t address;
- unsigned long alternate;
+ u32 address;
+ u32 alternate;
};
- unsigned long pio_words[DMA_PIO_WORDS];
+ u32 pio_words[DMA_PIO_WORDS];
};
/*
@@ -117,7 +118,7 @@ struct mxs_dma_cmd {
struct mxs_dma_desc {
struct mxs_dma_cmd cmd;
unsigned int flags;
- dma_addr_t address;
+ u32 address;
void *buffer;
struct list_head node;
} __aligned(MXS_DMA_ALIGNMENT);
diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
index 907e7ed8f9..74c9031d4e 100644
--- a/arch/arm/include/asm/mach-imx/imx-nandbcb.h
+++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
@@ -9,9 +9,11 @@
#define FCB_FINGERPRINT 0x20424346 /* 'FCB' */
#define FCB_VERSION_1 0x01000000
+#define FCB_FINGERPRINT_OFF 0x4 /* FCB fingerprint offset*/
-#define DBBT_FINGERPRINT2 0x54424244 /* 'DBBT' */
+#define DBBT_FINGERPRINT 0x54424244 /* 'DBBT' */
#define DBBT_VERSION_1 0x01000000
+#define DBBT_FINGERPRINT_OFF 0x4 /* DBBT fingerprint offset*/
struct dbbt_block {
u32 checksum; /* reserved on i.MX6 */
diff --git a/arch/arm/include/asm/mach-imx/module_fuse.h b/arch/arm/include/asm/mach-imx/module_fuse.h
new file mode 100644
index 0000000000..a46fc3f1f8
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/module_fuse.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __MODULE_FUSE_H__
+#define __MODULE_FUSE_H__
+
+enum fuse_module_type {
+ MODULE_TSC,
+ MODULE_ADC1,
+ MODULE_ADC2,
+ MODULE_SIM1,
+ MODULE_SIM2,
+ MODULE_FLEXCAN1,
+ MODULE_FLEXCAN2,
+ MODULE_SPDIF,
+ MODULE_EIM,
+ MODULE_SD1,
+ MODULE_SD2,
+ MODULE_SD3,
+ MODULE_SD4,
+ MODULE_QSPI1,
+ MODULE_QSPI2,
+ MODULE_GPMI,
+ MODULE_APBHDMA,
+ MODULE_LCDIF,
+ MODULE_PXP,
+ MODULE_CSI,
+ MODULE_ENET1,
+ MODULE_ENET2,
+ MODULE_CAAM,
+ MODULE_USB_OTG1,
+ MODULE_USB_OTG2,
+ MODULE_SAI2,
+ MODULE_SAI3,
+ MODULE_BEE,
+ MODULE_UART1,
+ MODULE_UART2,
+ MODULE_UART3,
+ MODULE_UART4,
+ MODULE_UART5,
+ MODULE_UART6,
+ MODULE_UART7,
+ MODULE_UART8,
+ MODULE_PWM5,
+ MODULE_PWM6,
+ MODULE_PWM7,
+ MODULE_PWM8,
+ MODULE_ECSPI1,
+ MODULE_ECSPI2,
+ MODULE_ECSPI3,
+ MODULE_ECSPI4,
+ MODULE_ECSPI5,
+ MODULE_I2C1,
+ MODULE_I2C2,
+ MODULE_I2C3,
+ MODULE_I2C4,
+ MODULE_GPT1,
+ MODULE_GPT2,
+ MODULE_EPIT1,
+ MODULE_EPIT2,
+ MODULE_EPDC,
+ MODULE_ESAI,
+ MODULE_DCP,
+ MODULE_DCP_CRYPTO,
+};
+
+struct fuse_entry_desc {
+ enum fuse_module_type module;
+ const char *node_path;
+ u32 fuse_word_offset;
+ u32 fuse_bit_offset;
+ u32 status;
+};
+
+#if !CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
+static inline u32 check_module_fused(enum fuse_module_type module)
+{
+ return 0;
+};
+
+static inline u32 esdhc_fused(ulong base_addr)
+{
+ return 0;
+};
+
+static inline u32 ecspi_fused(ulong base_addr)
+{
+ return 0;
+};
+
+static inline u32 uart_fused(ulong base_addr)
+{
+ return 0;
+};
+
+static inline u32 usb_fused(ulong base_addr)
+{
+ return 0;
+};
+
+static inline u32 qspi_fused(ulong base_addr)
+{
+ return 0;
+};
+
+static inline u32 i2c_fused(ulong base_addr)
+{
+ return 0;
+};
+
+static inline u32 enet_fused(ulong base_addr)
+{
+ return 0;
+};
+#else
+u32 check_module_fused(enum fuse_module_type module);
+u32 esdhc_fused(ulong base_addr);
+u32 ecspi_fused(ulong base_addr);
+u32 uart_fused(ulong base_addr);
+u32 usb_fused(ulong base_addr);
+u32 qspi_fused(ulong base_addr);
+u32 i2c_fused(ulong base_addr);
+u32 enet_fused(ulong base_addr);
+#endif
+#endif /* __MODULE_FUSE_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h
index d7baf13343..94c330c7f9 100644
--- a/arch/arm/include/asm/mach-imx/regs-apbh.h
+++ b/arch/arm/include/asm/mach-imx/regs-apbh.h
@@ -7,6 +7,7 @@
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2020 NXP
*/
#ifndef __REGS_APBH_H__
@@ -95,7 +96,7 @@ struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_version)
};
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#else
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
@@ -274,7 +275,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
@@ -357,7 +358,6 @@ struct mxs_apbh_regs {
#if defined(CONFIG_MX28)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
-#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
@@ -390,9 +390,8 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+/* Not on i.MX23 */
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
-#endif
#if defined(CONFIG_MX23)
#define APBH_DEVSEL_CH7_MASK (0xf << 28)
diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h
index 39ac5f4d45..5a149002e2 100644
--- a/arch/arm/include/asm/mach-imx/regs-bch.h
+++ b/arch/arm/include/asm/mach-imx/regs-bch.h
@@ -6,7 +6,9 @@
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2020 NXP
+ *
*/
#ifndef __MX28_REGS_BCH_H__
@@ -40,6 +42,7 @@ struct mxs_bch_regs {
mxs_reg_32(hw_bch_dbgahbmread)
mxs_reg_32(hw_bch_blockname)
mxs_reg_32(hw_bch_version)
+ mxs_reg_32(hw_bch_debug1)
};
#endif
@@ -75,6 +78,9 @@ struct mxs_bch_regs {
#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
+#define BCH_MODE_ERASE_THRESHOLD(v) \
+ (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \
+ BCH_MODE_ERASE_THRESHOLD_MASK)
#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
#define BCH_ENCODEPTR_ADDR_OFFSET 0
@@ -122,7 +128,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
@@ -146,14 +152,14 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
-#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK BIT(10)
#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
-#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff
#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
@@ -177,9 +183,9 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
-#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
+#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK BIT(10)
#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
-#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
+#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff
#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 2a997f280d..927195f87a 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/mach-imx/regs-common.h>
+#include <asm/mach-imx/module_fuse.h>
#include <common.h>
#include "../arch-imx/cpu.h"
@@ -197,4 +198,6 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
unsigned long *reg1, unsigned long reg2,
unsigned long reg3);
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#endif
generated by cgit (git 2.34.1) at 2025-01-06 12:06:38 +0000