diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-imx/cpu.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 10 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/crm_regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/sys_proto.h | 5 |
4 files changed, 7 insertions, 12 deletions
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 75ff991248..f37fe21446 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -41,9 +41,7 @@ #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ #define MXC_CPU_IMX8MP 0x182/* dummy ID */ -#define MXC_CPU_IMX8MP7 0x183 /* dummy ID */ #define MXC_CPU_IMX8MP6 0x184 /* dummy ID */ -#define MXC_CPU_IMX8MP5 0x185 /* dummy ID */ #define MXC_CPU_IMX8MPL 0x186 /* dummy ID */ #define MXC_CPU_IMX8MPD 0x187 /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 742cbf3bf8..340a61e55b 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -316,7 +316,7 @@ enum clk_src_index { #define FRAC_PLL_LOCK_MASK BIT(31) #define FRAC_PLL_CLKE_MASK BIT(21) #define FRAC_PLL_PD_MASK BIT(19) -#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) +#define FRAC_PLL_REFCLK_SEL_MASK (0x3 << 16) #define FRAC_PLL_LOCK_SEL_MASK BIT(15) #define FRAC_PLL_BYPASS_MASK BIT(14) #define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) @@ -358,10 +358,10 @@ enum clk_src_index { #define SSCG_PLL_LOCK_SEL_MASK BIT(3) #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) #define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0) +#define SSCG_PLL_REFCLK_SEL_OSC_27M (1) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3) #define SSCG_PLL_SSDS_MASK BIT(8) #define SSCG_PLL_SSMD_MASK (0x7 << 5) diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index f3515fab03..bfa68a9d2a 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -57,7 +57,7 @@ struct mxc_ccm_reg { uint32_t reserved_0[4092]; struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ uint32_t reserved_1[3332]; - struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ + struct mxc_ccm_root_slice root[125]; /* offset 0x8000 */ }; diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 15d1cba8e7..5f0c1ae218 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -67,13 +67,10 @@ struct bd_info; #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ - is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \ - is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5)) + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) -#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7)) #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) -#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) |