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-rw-r--r--arch/arm/include/asm/arch-bcm235xx/boot0.h2
-rw-r--r--arch/arm/include/asm/arch-bcm281xx/boot0.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/boot0.h38
-rw-r--r--arch/arm/include/asm/arch-rockchip/boot_mode.h6
-rw-r--r--arch/arm/include/asm/arch-rockchip/bootrom.h30
-rw-r--r--arch/arm/include/asm/arch-rockchip/clock.h5
-rw-r--r--arch/arm/include/asm/setjmp.h94
-rw-r--r--arch/arm/include/asm/system.h62
8 files changed, 112 insertions, 127 deletions
diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h
index a747bd3823..28f05ba32d 100644
--- a/arch/arm/include/asm/arch-bcm235xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h
@@ -5,5 +5,7 @@
*/
/* BOOT0 header information */
+_start:
+ ARM_VECTORS
.word 0xbabeface
.word _end - _start
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h
index a747bd3823..28f05ba32d 100644
--- a/arch/arm/include/asm/arch-bcm281xx/boot0.h
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -5,5 +5,7 @@
*/
/* BOOT0 header information */
+_start:
+ ARM_VECTORS
.word 0xbabeface
.word _end - _start
diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
index 72d264bcbe..af3a733e98 100644
--- a/arch/arm/include/asm/arch-rockchip/boot0.h
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -1,4 +1,3 @@
-
/*
* Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
@@ -7,26 +6,49 @@
/*
* Execution starts on the instruction following this 4-byte header
- * (containing the magic 'RK33').
+ * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
+ * magic constant will be written into the final image by the rkimage
+ * tool, but we need to reserve space for it here.
*
* To make life easier for everyone, we build the SPL binary with
* space for this 4-byte header already included in the binary.
*/
-
#ifdef CONFIG_SPL_BUILD
/*
* We need to add 4 bytes of space for the 'RK33' at the
* beginning of the executable. However, as we want to keep
* this generic and make it applicable to builds that are like
* the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
- * TPL, but extra space needed in the SPL), we simply repeat
- * the 'b reset' with the expectation that the first one will
- * be overwritten, if this is the first stage contained in the
- * final image created with mkimage)...
+ * TPL, but extra space needed in the SPL), we simply insert
+ * a branch-to-next-instruction-word with the expectation that
+ * the first one may be overwritten, if this is the first stage
+ * contained in the final image created with mkimage)...
*/
- b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
+ b 1f /* if overwritten, entry-address is at the next word */
+1:
+#endif
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+ adr r3, entry_counter
+ ldr r0, [r3]
+ cmp r0, #1 /* check if entry_counter == 1 */
+ beq reset /* regular bootup */
+ add r0, #1
+ str r0, [r3] /* increment the entry_counter in memory */
+ mov r0, #0 /* return 0 to the BROM to signal 'OK' */
+ bx lr /* return control to the BROM */
+entry_counter:
+ .word 0
#endif
b reset
+#if !defined(CONFIG_ARM64)
+ /*
+ * For armv7, the addr '_start' will used as vector start address
+ * and write to VBAR register, which needs to aligned to 0x20.
+ */
+ .align(5), 0x0
+_start:
+ ARM_VECTORS
+#endif
#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h
index bd65f60bf2..6b2a610cf4 100644
--- a/arch/arm/include/asm/arch-rockchip/boot_mode.h
+++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -15,5 +15,11 @@
#define BOOT_CHARGING (REBOOT_FLAG + 11)
/* enter usb mass storage mode */
#define BOOT_UMS (REBOOT_FLAG + 12)
+/* enter bootrom download mode */
+#define BOOT_BROM_DOWNLOAD 0xEF08A53C
+
+#ifndef __ASSEMBLY__
+int setup_boot_mode(void);
+#endif
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 169cc5e50b..103b799593 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -14,15 +15,30 @@
extern u32 SAVE_SP_ADDR;
/**
- * Hand control back to the bootrom to load another
- * boot stage.
+ * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a
+ * result code
+ *
+ * Transfer control back to the Rockchip BROM, restoring necessary
+ * register context and passing a command/result code to the BROM
+ * to instruct its next actions (e.g. continue boot sequence, enter
+ * download mode, ...).
+ *
+ * This function does not return.
+ *
+ * @brom_cmd: indicates how the bootrom should continue the boot
+ * sequence (e.g. load the next stage)
*/
-void back_to_bootrom(void);
+enum rockchip_bootrom_cmd {
+ /*
+ * These can not start at 0, as 0 has a special meaning
+ * for setjmp().
+ */
-/**
- * Assembler component for the above (do not call this directly)
- */
-void _back_to_bootrom_s(void);
+ BROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */
+ BROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */
+};
+
+void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd);
/**
* Boot-device identifiers as used by the BROM
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 641df58ac2..736b2603fd 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -39,6 +39,11 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
return clk_id - 1;
}
+struct sysreset_reg {
+ unsigned int glb_srst_fst_value;
+ unsigned int glb_srst_snd_value;
+};
+
/**
* clk_get_divisor() - Calculate the required clock divisior
*
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
index c3399a7e15..517beebdea 100644
--- a/arch/arm/include/asm/setjmp.h
+++ b/arch/arm/include/asm/setjmp.h
@@ -1,6 +1,6 @@
/*
- * (C) Copyright 2016
- * Alexander Graf <agraf@suse.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ * (C) Copyright 2016 Alexander Graf <agraf@suse.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,89 +8,21 @@
#ifndef _SETJMP_H_
#define _SETJMP_H_ 1
+/*
+ * This really should be opaque, but the EFI implementation wrongly
+ * assumes that a 'struct jmp_buf_data' is defined.
+ */
struct jmp_buf_data {
- ulong target;
- ulong regs[5];
- int ret;
-};
-
-typedef struct jmp_buf_data jmp_buf[1];
-
-static inline int setjmp(jmp_buf jmp)
-{
- jmp->ret = 0;
-
-#ifdef CONFIG_ARM64
- asm volatile(
- "adr x1, jmp_target\n"
- "str x1, %0\n"
- "stp x26, x27, %1\n"
- "stp x28, x29, %2\n"
- "mov x1, sp\n"
- "str x1, %3\n"
- "jmp_target: "
- : "=m" (jmp->target), "=m" (jmp->regs[0]),
- "=m" (jmp->regs[2]), "=m" (jmp->regs[4])
- :
- : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
- "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
- "x16", "x17", "x18", "x19", "x20", "x21", "x22",
- "x23", "x24", "x25", /* x26, x27, x28, x29, sp */
- "x30", "cc", "memory");
-#else
- asm volatile(
-#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
- ".align 2\n"
- "adr r0, jmp_target\n"
- "add r0, r0, $1\n"
+#if defined(__aarch64__)
+ u64 regs[13];
#else
- "adr r0, jmp_target\n"
-#endif
- "mov r1, %0\n"
- "mov r2, sp\n"
- "stm r1!, {r0, r2, r4, r5, r6, r7}\n"
- ".align 2\n"
- "jmp_target: \n"
- :
- : "l" (&jmp->target)
- : "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */
- "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr",
- "cc", "memory");
-#endif
-
- return jmp->ret;
-}
-
-static inline __noreturn void longjmp(jmp_buf jmp, int ret)
-{
- jmp->ret = ret;
-
-#ifdef CONFIG_ARM64
- asm volatile(
- "ldr x0, %0\n"
- "ldr x1, %3\n"
- "mov sp, x1\n"
- "ldp x26, x27, %1\n"
- "ldp x28, x25, %2\n"
- "mov x29, x25\n"
- "br x0\n"
- :
- : "m" (jmp->target), "m" (jmp->regs[0]), "m" (jmp->regs[2]),
- "m" (jmp->regs[4])
- : "x0", "x1", "x25", "x26", "x27", "x28");
-#else
- asm volatile(
- "mov r1, %0\n"
- "ldm r1!, {r0, r2, r4, r5, r6, r7}\n"
- "mov sp, r2\n"
- "bx r0\n"
- :
- : "l" (&jmp->target)
- : "r1");
+ u32 regs[10]; /* r4-r9, sl, fp, sp, lr */
#endif
+};
- while (1) { }
-}
+typedef struct jmp_buf_data jmp_buf[1];
+int setjmp(jmp_buf jmp);
+void longjmp(jmp_buf jmp, int ret);
#endif /* _SETJMP_H_ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1d7d4f35c4..4f043cad0b 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -332,37 +332,6 @@ void psci_arch_init(void);
#ifndef __ASSEMBLY__
-/**
- * save_boot_params() - Save boot parameters before starting reset sequence
- *
- * If you provide this function it will be called immediately U-Boot starts,
- * both for SPL and U-Boot proper.
- *
- * All registers are unchanged from U-Boot entry. No registers need be
- * preserved.
- *
- * This is not a normal C function. There is no stack. Return by branching to
- * save_boot_params_ret.
- *
- * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
- */
-
-/**
- * save_boot_params_ret() - Return from save_boot_params()
- *
- * If you provide save_boot_params(), then you should jump back to this
- * function when done. Try to preserve all registers.
- *
- * If your implementation of save_boot_params() is in C then it is acceptable
- * to simply call save_boot_params_ret() at the end of your function. Since
- * there is no link register set up, you cannot just exit the function. U-Boot
- * will return to the (initialised) value of lr, and likely crash/hang.
- *
- * If your implementation of save_boot_params() is in assembler then you
- * should use 'b' or 'bx' to return to save_boot_params_ret.
- */
-void save_boot_params_ret(void);
-
#ifdef CONFIG_ARMV7_LPAE
void switch_to_hypervisor_ret(void);
#endif
@@ -556,6 +525,37 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
#ifndef __ASSEMBLY__
/**
+ * save_boot_params() - Save boot parameters before starting reset sequence
+ *
+ * If you provide this function it will be called immediately U-Boot starts,
+ * both for SPL and U-Boot proper.
+ *
+ * All registers are unchanged from U-Boot entry. No registers need be
+ * preserved.
+ *
+ * This is not a normal C function. There is no stack. Return by branching to
+ * save_boot_params_ret.
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
+ */
+
+/**
+ * save_boot_params_ret() - Return from save_boot_params()
+ *
+ * If you provide save_boot_params(), then you should jump back to this
+ * function when done. Try to preserve all registers.
+ *
+ * If your implementation of save_boot_params() is in C then it is acceptable
+ * to simply call save_boot_params_ret() at the end of your function. Since
+ * there is no link register set up, you cannot just exit the function. U-Boot
+ * will return to the (initialised) value of lr, and likely crash/hang.
+ *
+ * If your implementation of save_boot_params() is in assembler then you
+ * should use 'b' or 'bx' to return to save_boot_params_ret.
+ */
+void save_boot_params_ret(void);
+
+/**
* Change the cache settings for a region.
*
* \param start start address of memory region to change