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-rw-r--r--arch/arm/mach-imx/cpu.c4
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mm.c1
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c12
-rw-r--r--arch/arm/mach-imx/mx6/ddr.c15
4 files changed, 20 insertions, 12 deletions
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index fe8d5947cc..4a175cb86f 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -102,12 +102,8 @@ const char *get_imx_type(u32 imxtype)
return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
case MXC_CPU_IMX8MPL:
return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
- case MXC_CPU_IMX8MP7:
- return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */
case MXC_CPU_IMX8MP6:
return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
- case MXC_CPU_IMX8MP5:
- return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */
case MXC_CPU_IMX8MN:
return "8MNano Quad"; /* Quad-core version */
case MXC_CPU_IMX8MND:
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 3610f5b2fc..9dde11cded 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -360,6 +360,7 @@ void init_clk_ecspi(u32 index)
clock_enable(CCGR_ECSPI2, 0);
clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_ECSPI2, 1);
+ return;
case 2:
clock_enable(CCGR_ECSPI3, 0);
clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8dfc8645fc..9bca5bf972 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -343,12 +343,8 @@ static u32 get_cpu_variant_type(u32 type)
switch (flag) {
case 7:
return MXC_CPU_IMX8MPL;
- case 6:
- return MXC_CPU_IMX8MP5;
case 2:
return MXC_CPU_IMX8MP6;
- case 1:
- return MXC_CPU_IMX8MP7;
default:
break;
}
@@ -889,16 +885,16 @@ usb_modify_speed:
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
- if (is_imx8mpl() || is_imx8mp7())
+ if (is_imx8mpl())
disable_vpu_nodes(blob);
- if (is_imx8mpl() || is_imx8mp6() || is_imx8mp5())
+ if (is_imx8mpl() || is_imx8mp6())
disable_npu_nodes(blob);
- if (is_imx8mpl() || is_imx8mp5())
+ if (is_imx8mpl())
disable_isp_nodes(blob);
- if (is_imx8mpl() || is_imx8mp7() || is_imx8mp6() || is_imx8mp5())
+ if (is_imx8mpl() || is_imx8mp6())
disable_dsp_nodes(blob);
if (is_imx8mpd())
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 16df71083d..f872bfdab3 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -250,16 +250,31 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
static void mmdc_set_sdqs(bool set)
{
+ struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
+ (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
(struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+ struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
+ (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
+ struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
+ (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
int i, sdqs_cnt;
u32 sdqs;
if (is_mx6sx()) {
sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
+ } else if (is_mx6sl()) {
+ sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 2;
+ } else if (is_mx6ul() || is_mx6ull()) {
+ sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 2;
+ } else if (is_mx6sdl()) {
+ sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 8;
} else { /* MX6DQ */
sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
sdqs_cnt = 8;