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-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/imx8/Kconfig11
-rw-r--r--arch/arm/mach-imx/imx8/cpu.c3
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c7
-rw-r--r--arch/arm/mach-imx/lowlevel.S22
-rw-r--r--arch/arm/mach-imx/mx2/Kconfig2
-rw-r--r--arch/arm/mach-imx/mx5/Kconfig4
-rw-r--r--arch/arm/mach-imx/mx6/Kconfig12
-rw-r--r--arch/arm/mach-imx/sip.c22
9 files changed, 83 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c3ed62aed6..37675d0558 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -204,7 +204,7 @@ endif
targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
-obj-$(CONFIG_ARM64) += sip.o
+obj-$(CONFIG_ARM64) += lowlevel.o sip.o
obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index f76a139684..c32f7dbb61 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -10,6 +10,11 @@ config MU_BASE_SPL
SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
So we could not reuse the one in dts which is for normal U-Boot.
+config IMX8QM
+ select IMX8
+ select SUPPORT_SPL
+ bool
+
config IMX8QXP
select IMX8
select SUPPORT_SPL
@@ -27,8 +32,14 @@ config TARGET_IMX8QXP_MEK
select BOARD_LATE_INIT
select IMX8QXP
+config TARGET_IMX8QM_MEK
+ bool "Support i.MX8QM MEK board"
+ select BOARD_LATE_INIT
+ select IMX8QM
+
endchoice
source "board/freescale/imx8qxp_mek/Kconfig"
+source "board/freescale/imx8qm_mek/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 4bbc956f9d..2c425357b5 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -542,6 +542,8 @@ const char *get_imx8_type(u32 imxtype)
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "QXP";
+ case MXC_CPU_IMX8QM:
+ return "QM";
default:
return "??";
}
@@ -613,6 +615,7 @@ static const struct cpu_ops cpu_imx8_ops = {
static const struct udevice_id cpu_imx8_ids[] = {
{ .compatible = "arm,cortex-a35" },
+ { .compatible = "arm,cortex-a53" },
{ }
};
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 11251c5f9a..7ec39b3e47 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -169,6 +169,7 @@ static void imx_set_wdog_powerdown(bool enable)
int arch_cpu_init(void)
{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
* Init timer at very early state, because sscg pll setting
* will use it
@@ -180,6 +181,12 @@ int arch_cpu_init(void)
imx_set_wdog_powerdown(false);
}
+ if (is_imx8mq()) {
+ clock_enable(CCGR_OCOTP, 1);
+ if (readl(&ocotp->ctrl) & 0x200)
+ writel(0x200, &ocotp->ctrl_clr);
+ }
+
return 0;
}
diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S
new file mode 100644
index 0000000000..158fdb7d87
--- /dev/null
+++ b/arch/arm/mach-imx/lowlevel.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ mrs x0, CurrentEL
+ cmp x0, #8
+ b.eq 1f
+ ret
+1:
+ msr daifclr, #4
+
+ /* set HCR_EL2.AMO to catch SERROR */
+ mrs x0, hcr_el2
+ orr x0, x0, #0x20
+ msr hcr_el2, x0
+ isb
+ ret
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig
index ea308fccab..30a331ae43 100644
--- a/arch/arm/mach-imx/mx2/Kconfig
+++ b/arch/arm/mach-imx/mx2/Kconfig
@@ -17,7 +17,7 @@ config TARGET_MX25PDK
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
- select CPU_ARM926EJS1
+ select CPU_ARM926EJS
endchoice
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 29051c40f3..bde37bb97e 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -27,6 +27,10 @@ config TARGET_KP_IMX53
select DM_I2C
select DM_PMIC
select DM_SERIAL
+ select DM_MMC
+ select BLK
+ select DM_USB
+ select DM_REGULATOR
select MX53
imply CMD_DM
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index e782859b1e..f513c4c06f 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -161,6 +161,18 @@ config TARGET_COLIBRI_IMX6ULL
select DM_THERMAL
select MX6ULL
+config TARGET_DART_6UL
+ bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
+ select MX6ULL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_SERIAL
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_DHCOMIMX6
bool "dh_imx6"
select BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-imx/sip.c b/arch/arm/mach-imx/sip.c
index 813c2ae5e1..968e7cf309 100644
--- a/arch/arm/mach-imx/sip.c
+++ b/arch/arm/mach-imx/sip.c
@@ -20,3 +20,25 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
return regs.regs[0];
}
+
+/*
+ * Do an SMC call to return 2 registers by having reg1 passed in by reference
+ */
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+ unsigned long *reg1, unsigned long reg2,
+ unsigned long reg3)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = id;
+ regs.regs[1] = reg0;
+ regs.regs[2] = *reg1;
+ regs.regs[3] = reg2;
+ regs.regs[4] = reg3;
+
+ smc_call(&regs);
+
+ *reg1 = regs.regs[1];
+
+ return regs.regs[0];
+}